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Formal Bit With Determination for Nested Loop Programs

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High level synthesis (hardware compilation from functional specification) How to go (safely) from algorithmic description to ... Perron-Frobenius for (max, ... – PowerPoint PPT presentation

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Title: Formal Bit With Determination for Nested Loop Programs


1
Formal Bit With Determination for Nested Loop
Programs
  • David Cachera,
  • Tanguy Risset,
  • Djamel Zegaoui

2
Outline
  • Introduction/motivation
  • Explaining the methodology
  • Solving the Bit Width equation with (max,)

3
Context and Motivations
  • Context
  • High level synthesis (hardware compilation from
    functional specification)
  • How to go (safely) from algorithmic description
    to finite precision implementation
  • Specific motivations
  • Parameterized loop nests programs
  • MMAlpha methodology

4
Context and Motivations MMAlpha
  • Provide a formal methodology based on the strong
    semantic properties of the Alpha language
  • But still ! Keep applicability for effective VHDL
    generation

5
BW determination state of the art
  • Formal methods
  • Provide abstract framework for solving the
    problem (Gaut, Ptolemy, DeepC)
  • Limited applicability
  • Simulation based methods
  • Based on probabilistic models for input data
    (Ptolemy, Imec,etc.)
  • Time consuming processes
  • Ideally provide formal methods to speed up the
    simulation.

6
Our methodology
  • Start from loop nest specification (in Alpha)
  • Schedule and Place (SIMD-like specification)
  • Bit Width determination
  • problem modeling
  • BW equation generation
  • BW equation solving
  • Hardware generation (VHDL)

7
Example the FIR !
system fir N,M 3ltNltM-1 (x n
1ltnltM of integer w i 0ltiltN-1 of
integer) returns (res n NltnltM of
integer) var Y n,i NltnltM -1ltiltN-1
of integer let Yn,i case i-1
0 0lti Yn,i-1 wi xn-i
esac resn Yn,N-1 tel
8
Problem modeling error signal
  •  Formal  signal s(n), implementation (n)
  • Noise signal e(n)s(n)- (n)
  • Noise Standard deviation
  • Signal to Noise ratio (SNR)
  • Good bit width if Rs is greater than a given
    value

9
Operators modeling Tou99
  • Let X be a signal encoded on mn1 bits
  • Generated error where q2-n
  • Error propagation
  • Addition
  • Multiplication

10
Architectural description in Alpha
Wt,p case tp1 wt-1
p2ltt Wt-1,p esac XPt,p
case p0 xtN-1
1ltp XPt-2,p-1 esac Yt,p case
p-1 0 0ltp
Yt-1,p-1 Wt-1,p XPt-1,p esac
11
Generation of BW equation
  • Simple projection of Alpha equation on space (p
    index) (BWA?A2)

Wt,p case tp1 wt-1
p2ltt Wt-1,p esac XPt,p
case p0 xtN-1
1ltp XPt-2,p-1 esac Yt,p case
p-1 0 0ltp
Yt-1,p-1 Wt-1,p XPt-1,p esac
BWWp Max( BWw BWWp) BWXPp case
p0 BWx 1ltp BWXPp-1
esac BWYp case p-1 0
0ltp q2/12max(BWYp-1 q2/12,
BWWXPpq2/12) esac
12
Solving the BW equations (FIR)
  • Here the solution can be easily provided by a
    symbolic solver (q2-n)

13
Solving the BW equations...
  • In general, we solve successively the strongly
    connected component of the reduced dependence
    graph

input
input
W
X
V2
V1
Y
V3
Fir (3 SCC)
Other example 1 SCC
14
Solving BW Eq for 1 SCC
BWV1p case p0 ?0 pgt1
max(BWV1p-1 ?, BWV3p-1 ?)
esac BWV2p case p0 ?0
1ltp max(BWV2p-1 ?, BWV3p-1 ?)
esac BWV3p case p0 ?0
1ltp max(BWV1p-1 ?, BWV2p-1
?) esac
V1t,p case p0 Input
pgt1 V1t-1,p-1- V3t-2,p-1 esac
V2t,p case p0 Input
1ltp V2t-2,p-1 V3t-1,p-1 esac
V3t,p case p0 Input
1ltp V1t-1,p-1 V2t-3,p-1 esac
15
Solving the BW equations...
  • General form (under some assumptions) of the BW
    equation for one SCC with k variables (for
    i1..k)
  • Example

16
Using (max,) notations
  • ? is the max and ? is the addition
  • Or

17
Perron-Frobenius for (max,)
  • Let M?Rmaxn?n be an irreducible matrix in (max,)
    with spectral ray ?M and cyclicity c(M), there
    exist an integer N such that
  • Here c(M)1, ?M ? and N1

18
Result
  • If we respect our restrictions, we are able to
    solve, in a parametric way the bit Width
    equations for a loop nest program.
  • This is the only method that solves this problem
    in a parametric way (MIT did something with DeepC
    but they do not handle symbolic parameters)

19
Restrictions of our methodology
  • Linear array architecture
  • BW equation solvable (i.e. no auto-adaptive
    mechanism or complicated convergence property)
  • No multiplication in strongly connected component
    of the graph

a0x Do i1,N aiai-1ai-1 Enddo
20
Conclusion
  • First method for parameterized loop nest bit
    width determination
  • Allow reducing the time needed for simulation
    (probably not much more than previous methods
    did)
  • New typing mechanism introduced in Alpha
  • IntegerS,8
  • IntegerS,3,6
  • C Mul8x8-12(A,B)
  • B Trunc(C,11)

21
Processor variable dependent BW
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