Development and Verification of Parameterized Digital Signal Processing Macros for Microelectronic S

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Development and Verification of Parameterized
Digital Signal Processing Macros for
Microelectronic Systems

• Presented By
• Adam Miller

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Overview

• Introduction
• Background Information
• Implementation
• Results
• Conclusions and Future Work

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1.1 Digital Systems

• Speed and Capacity
• Increasing Complexity
• Longer Design Times
• Increased Costs
• Time to Market

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1.1 Digital Systems, cont.

• Engineers per Project
• Design for Reuse
• Build on Existing Designs
• Flexible Designs
• Library of Designs

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1.2 Verification

• Testing
• Every Step of Design Process
• Reduce Errors
• Reduce Time Spent Correcting Errors

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1.3 Digital Signal Processing

• Sampling
• Time Domain Representation
• Converting to Frequency Domain
• Fast Fourier Transform (FFT)
• Frequency Domain Representation

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1.4 Research Goals

• Develop a Parameterized FFT
• Verification
• Rounders as Simple Example

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2. Background

• Design for Reuse in VHDL
• DSP
• Verification

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2.1 Design for Reuse in VHDL

• generic Statement
• generate Statement
• Conditional generates
• Loop generates

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2.1 Design for Reuse, cont.

• generic example
• entity shiftregN is
• generic( data_width integer 25
• n integer 4)
• port( clock, resetn in std_logic
• write_data in std_logic_vector(data_width-1
  downto 0)
• read_data out std_logic_vector(data_width-1
  downto 0))

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2.1 Design for Reuse, cont.

• Conditional Generate Example
• assign_a if a_in1 generate
• YltA
• end generate assign_a
• assign_b if a_in/1 generate
• YltB
• end generate assign_b

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2.2 DSP Overview

• Digital Signal Processing (DSP)
• Sampling
• Time Domain vs. Frequency Domain
• Fast Fourier Transform

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2.3 Butterfly Structure

• FFT Butterfly Structure

2-point input
2-point output

xS
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2.4 Verification

• Bit-True Modeling
• Time to Develop
• Algorithm Errors
• Exact Match
• Approximate
• Comparison, Results Not Exact
• Shorter Time to Develop
• Already Existing

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2.4 Verification, cont.

• Simulation
• Event Driven
• Timing Driven
• Testing
• External Hardware
• On-chip, BIST

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2.4 Verification, cont.

• Example BIST Design

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3.1 Rounder Implementation

• Three Levels of Hierarchy
• Output Gain Stage Highest Level
• Configurable Rounder
• Fixed Rounder Lowest Level
• Increasing Functionality
• Parameterized to Increase Flexibility

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3. Implementation

• Fixed Rounder
• Configurable Rounder
• Output Gain Stage
• FFT

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3.2 Fixed Rounder

• Parameters
• input_width
• output_width
• fr_rad_pos
• ri, ro, and rt
• Functionality
• Signed Numbers
• Overflow

• Signals
• d_in
• q_out

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3.3 Configurable Rounder

• Parameters
• input_width
• output_width
• rndr_sel_width
• cr_rad_pos
• ri, ro, rc, and rt
• Functionality
• Shifting Input

• Signals
• d_in
• q_out
• cr_rndr_sel

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3.4 Output Gain Stage

• Additional Parameters
• gain_width
• fr_rad_pos
• pr
• Functionality
• Configurable Rounder ? Multiplier ? Fixed Rounder

• Signals
• d_in
• q_out
• cr_rndr_sel
• gain

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3.5 FFT Overview

• Radix 22 Single-path Delay Feedback (SDF)
• 2 Butterfly Types BF2I, BF2II
• Natural Order Input, Complex
• Bit-Reversed Order Output, Complex
• Parameters
• N
• input_width
• twiddle_width

• add_g
• mult_g

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3.6 Butterflies

• BF2I
• Passing Mode
• Active Mode
• Used in odd-numbered stages

• BF2II
• Passing Mode
• Active Mode
• t0
• t1
• Used in even-numbered stages
• Feeds into Complex Multiplier if not the last
  stage

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3.6 Stage Types
clock reset
clock reset
address
Last Stage
Shift Register
Shift Register
Twiddle ROM
BF2I
BF2II
Twiddle Multiply
prvs
to_next
prvs
to_next
s
t s
(i) BF2I stage stage_I
(ii) BF2II stage stage_II
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3.6 Twiddle Factors

• Different for each N
• Used to replace the xS in the normal Butterfly
  Structure
• MATLAB
• Generates only needed ROMS

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3.7 FFT Generation

• Loops for the Number of Stages -log2(N)
• Places each Stage
• Connects Multiplier to Correct ROM
• Connects Last Stage to Output

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4. Results

• Rounder Results
• FFT Results

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4.1 Fixed Rounder Results
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4.2 Configurable Rounder Results
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4.3 Output Gain Stage Results
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4.4 FFT Presynthesis
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4.5 FFT Prelayout
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4.6 FFT Results, N8
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4.7 FFT Results, N64
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4.8 FFT Results, N256
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4.9 FFT Results, N1024
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4.10 FFT Layout, N64
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4.11 Layout Results

• 64-point FFT
• 610.5 µm x 610.4 µm, 372649.2 µm2
• 159,074 Transistors
• 256-point FFT
• 455,305 Transistors
• 1024-point FFT
• 1,268,238 Transistors

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5.1 Conclusions

• FFT simulated successfully
• 64-point
• Varying N
• Rounders simulated successfully. Fixed Rounder
  parameters varied.

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5.2 Future Work

• FFT Flexibility
• Pipelining
• Automatic Growth
• Twiddle Factor Generation
• Comparative study of FFT algorithm vs. others
• Additional Parameterized Macros and Test Benches