PostPlacement Rewiring and Rebuffering by Exhaustive Search for Functional Symmetries

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Post-Placement Rewiring and Rebuffering by
Exhaustive Search for Functional Symmetries

• Kai-hui Chang, Igor L. Markov and Valeria Bertacco

University of Michigan at Ann Arbor
Nov. 7, 2005
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Improving Deep Submicron Layouts

• Technology trends
• Wire delay becomes dominant
• Routability is exacerbated
• Manufacturing defects in vias become significant
• Making wires short and uncrossing them
• Decreases delay, power consumption
• Improves routability and yield

Rewiring
Permutational Symmetry
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Optimization for Long Wires Buffering

• Buffering add buffers to drive long nets
• 70 gates will be buffers at 32nm Saxena04
• A buffer ? 2 inverters
• A single inverter is often enough

Phase-shift Symmetry
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Post-Placement Rewiring and Rebuffering
Rewiring
Rebuffering
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Post-Placement Rewiring and Rebuffering
Unified optimization is more powerful
g1
g1
Rewiring and Rebuffering
g2
g2
g5
g5
g3
g3
Composite Symmetry
g4
g4
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Our Contributions

• A comprehensive symmetry detector
• Detects more symmetries more optimization
  opportunities
• Scalable enough for rewiring applications
• Applications of symmetries to rewiring
• Wirelength reduction comparable to detailed
  placement and is orthogonal to it
• Long-range rewiring
• Find equivalent wires that are further apart
• Innovative algorithm for rebuffering

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Outline

• Symmetry detection
• Layout improvement
• Permutative rewiring
• Rebuffering
• Long-range rewiring
• Experimental results
• Conclusions

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Symmetries in Boolean Functions

• Functional (semantic) symmetry
• Preserves functional relationshipbetween
  inputs/outputs
• Syntactic symmetry
• Preserves a specific representationof the
  function like circuit, BDD, etc.
• Syntactic symmetries ? semantic symmetries
• Detecting all semantic symmetries is more
  difficult

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Previous Work Symmetry Detection

• BDD
• Limited to input symmetries
• Circuit
• Syntactic symmetries only
• Also used in rewiring C. W. Chang04
• Graph
• A permutation of vertices that maps edges to
  edges and preserves vertex colors

D. Moller93 A. Mishchenko03
C. W. Chang04 G. Wang03
P. T. Darga04
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2
Symmetries detected (3, 4) (4, 5)
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4
5
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Symmetry Detection for Boolean Functions Using
Graphs
z x XOR y

• Two vertices for an input andits complement
• Two vertices for an output and its complement
• One vertex for each minterm/maxterm
• Edges from term to inputs
• Edges from term to outputs
• Feed the graph to Saucy for symmetry detection

Saucy is the graph symmetry detector used in
this work Darga, DAC 04
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Two Symmetries Returned by Saucy
z x XOR y
z(8)
z(8)
z(9)
z(9)
t0(4)
t1(5)
t2(6)
t3(7)
t0(4)
t1(5)
t2(6)
t3(7)
x(0)
y(2)
x(0)
y(2)
x(1)
y(3)
x(1)
y(3)
x ? y
x ? x, z? z
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1. Permutative Rewiring Concept and Algorithm

• If swapping/negating some pins can improve a
  certain objective accept the change
• Algorithm

• Extract sub-circuits iterativelyfrom the circuit
• Detect symmetries in thesub-circuit

circuit
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1. Permutative Rewiring Concept and Algorithm

• If swapping/negating some pins can improve a
  certain objective accept the change
• Algorithm

• Extract sub-circuits iterativelyfrom the circuit
• Detect symmetries in thesub-circuit
• Try rewiring and see if wirelength(delay, power)
  is improved
• (a) Improved ?
• rewire
• (b) No improvement ?
• ignore the symmetry

circuit
sub-circuit
symmetric
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1. Permutative Rewiring Sub-circuit Extraction

• Symmetries in sub-circuits represent rewiring
  opportunities
• Windowing is used
• To ensure efficiencyof symmetry detection
• It is a trade-off between coverage, runtime and
  rewiring quality
• Equivalent pins are more likely to be on
• Gates that are connected to each other
• Gates that connect to other common gates

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1. Permutative Rewiring Sub-circuit Extraction
Techniques

• Depth first search (DFS) 1-4 gates
• Breadth first search (BFS) 3-4 gates
• Recursive bisection 4-8 gates
• Min-cut placer
• Bins contain cells that are tightly connected

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2. Rebuffering

• Goal
• Reduce area and power by removing unnecessary
  inverters
• Improve circuit timing by moving inverters to
  more/less critical nets
• Logic equivalence is preserved
• Our algorithm

• Given a buffer to be inserted
• Extract a sub-circuit involving the wire
• Search for phase-shift symmetry involving the
  wire

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2. Rebuffering

• Goal
• Reduce area and power by removing unnecessary
  inverters
• Improve circuit timing by moving inverters to
  more/less critical nets
• Logic equivalence is preserved
• Our algorithm

• Given a buffer to be inserted
• Extract a sub-circuit involving the wire
• Search for phase-shift symmetry involving the
  wire
• Rebuffer according to the symmetry

or
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3. Long-Range Rewiring

• Idea F. Lu04A. Mischenko05(FRAIG)
• Find equivalent wires that are further apart
• Further reduce wirelength by reconnecting
  equivalent wires
• Algorithm
• Use simulation to identify potentially
  equivalent wires
• Check for wirelength improvement
• CNF-SAT is used to prove the equivalence
• Equivalence checking can be pruned if no
  wirelength reduction can be gained

Equivalent
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3. Long-Range Rewiring Algorithm

• Simulate using random patterns
• Generate a signature for each wire (simulated
  values)
• For wires with identical signatures
• Try to reconnect them
• If wire is not shortened, abandon the
  reconnection
• If wire is shortened, use CNF-SAT solver to check
  equivalence, abandon the reconnection if not
  equivalent

010
010
110
1. Random simulation
3. Try to reconnect 4. Equivalence Checking
2. Possibly equivalent
011
010
111
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Experimental Setup

• Placer Capo. Symmetry detector Saucy
• Nodes and nets generated by blif2book.exe
  provided in the GSRC bookshelf
• The converter was enhanced to generate standard
  cells of different sizes
• e.g., NAND and BUF are 2x larger than INV
• Benchmarks

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Our Experiments
Globalplacer
Detailed placer
Nodes,nets
Global placement
Detailed placement
All netlist transformations were verified by
equivalence checking
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Experimental Results 1Number of Symmetries Found

• Symmetries represent potential for improvement
• Most previous works focus on input symmetries
• Phase-shift and output symmetries should also be
  exploited for better optimization

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Experimental Results 2 Performance of
Permutative Rewiring
Comparison between Rewiring and Detailed Placement
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Experimental Results 3 Performance of
Permutative Rewiring
Performance Comparison Before and After Detailed
Placement
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Experimental Results 4Performance of Long-Range
Rewiring
Long-Range Rewiring Before and After Permutative
Rewiring

• Long-range rewiring can further reduce wirelength
  and should be applied after permutative rewiring
• Cumulative wirelength reduction becomes 5.17
• 5 improvement is significant
• It is independent of other optimizations
• It does not require any changes in existing tools
• It leads to a comparable reduction in via counts
• For example, in b10, 5.7 reduction in number of
  vias is observed

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Summary of Experimental Results
Globalplacer
Detailed placer
Nodes,nets
Global placement
Detailed placement
Wirelength reductions from permutative rewiring
and detailed placement are similar
Long-range rewiring and permutative rewiring are
independent optimizations
Phase-shift and output symmetries should also be
utilized
Permutative rewiring and detailed placement are
independent optimizations
All netlist transformations were verified by
equivalence checking
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Discussion

• Advantages
• It does not change any placement
• It is safe and can be applied with every flow
• It can optimize a broad variety of objectives
• It considers both input and output symmetries
• E. g., in multi-bit adders order of inputs and
  outputs can be permuted, but only simultaneously
• Greater benefits when gates are larger and pins
  are further apart
• Limitations
• Performance depends on the benchmark
• Reduction ratio decreases when design gets larger
  similar to detailed placement

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Conclusions and Future Work

• Comprehensive detection of functional symmetries
  in small circuits
• Suitable for rewiring
• The more symmetries, the more optimization
  opportunities
• Permutative rewiring is effective and appears
  orthogonal to detailed placement
• Long-range rewiring can further reduce wirelength
• Overall wirelength reduction is 5.17
• Symmetry-based rebuffering proposed
• Better use of phase-shift symmetry