Integrated Systems Design Trends, Challenges and Solutions Global Workflow 2006 Seminar

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Integrated Systems DesignTrends, Challenges and
SolutionsGlobal Workflow 2006 Seminar

• Sami Aarras
• Team Leader, PWB Design Tools
• Mentor Graphics Finland

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Mentor Graphics

• Revenue - over 700 million in 2004
• Market Share 19 of worldwide EDA market
• Third ranking in EDA industry
• Focused on growth through internal development

Source EDAC Market Statistics
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Mentor Graphics Around the World
Operates through 28 engineering sites and 48
sales offices around the world
Key Sales Offices
RD Sites
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Mentors SystemsDesign Organization

• Delivers TOTAL flow solutions for Integrated
  Systems Design (ISD)
• Design content
• Design intent
• Analysis
• Verification
• FPGA Synthesis
• Manufacturing outputs
• Data management
• Harness Systems
• Worldwide PCB market share leader
• 400 employees

Source Dataquest June 2004
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Mentors Integrated Systems Design Focus
Package
Integration
Connectivity
Corporate Infrastructure Systems
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Integrated Systems Design Flow
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The Electronics Industry Faces Many Challenges

• Drive to reduce design cycle time and
  time-to-market
• Use of latest IC and PCB technology to compete
• Form factor
• Performance
• Leverage resources of a global enterprise
• Reduce product costs and increase margins
• Reliability and quality

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Systems Design Complexity on the Rise
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Business Pressures Continue
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Time-to-Market is Critical, but,
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.. Increasing Systems Design Complexity Lengthens
Design Cycle Time

• Design Complexities
• More high-complexity FPGAs on board
• Higher speed interconnects system performance
• Higher pin-count FPGA IC packages
• Consumer product use of flex rigid-flex
• HDI/Microvia layer fabrication
• Embedded components
• Industry globalization
• Outsourcing

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Continued Investment is Required to Counteract
Complexities

• Mentors Investment
• in Integrated Systems Design
• Reduced design cycle
• Use of advanced technologies
• Support for Global companies

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Electronics Industry Has Gone Global
Global companies have design teams, manufacturing
and outsource in locations worldwide.
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Challenges Faced By Large Global Companies

• Leveraging design teams located locally or
  globally dispersed
• Need to have the design follow-the-sun to cut
  design cycle time
• Expertise may exist in several locations (RF,
  digital, analog)
• Need to efficiently create, control and provide
  access to intellectual property on a global scale
• Design data
• Library data
• Design constraints, rules, information
• Provide seamless communication between OEM and
  outsourcees
• Electronic manufacturing suppliers (EMS)
• ODMs and third parties performing all of part of
  design process
• Protection and control of IP

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Global Design Teams
Local or globally dispersed design teams must be
able to work on the same design at the same time.
Goal Reduce design cycle time!
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Support for Global Design TeamsOn Large,
Complex Designs

• Solution Simultaneous layout by multiple
  designers

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Support for Global Design TeamsOn Mixed
Technology Designs

• Solution Simultaneous layout by technical
  specialists

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XtremePCB Design

• Multiple designers
• The same design
• The same application
• At the same time
• LAN or WAN enabled
• Edits automatically synchronized in real time
• Changes checked, merged, broadcasted
• For all PCB layout tasks
• Placement, routing, verification, drafting,
  manufacturing prep
• Value
• Significant reduction in layout design cycle time
  
• Enable globally dispersed design teams and
  specialists to work simultaneously on the same
  design

Designer
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Outsourcing Design
Many global companies outsource a part of their
design to 3rd party design houses or ODMs. Goal
capitalize on outsourced expertise.
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Adding to the Complexity!55 of Companies
Outsource All or Part of their Board Designs
Source EEtimes Research Report, January 2005
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Innovation in Global Team Design
Digital Designer

• TeamPCB
• Divide design into sections
• Layout sections in parallel
• Share progress with other designers
• Merge sections back into master design
• Totally automated error free

Analog Designer
Digital Designer
Master
Split Join
Designer-to-designer updates
RF Designer
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Managing Intellectual Property is a Challenge
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Intellectual Property

• What constitutes IP?
• Design data
• Re-useable blocks
• Library parts data
• Design constraint rules and design intent
  information
• What are the challenges?
• Efficient access and download of supply chain
  info.
• Searching and choosing the right component
• Capture, access and control of constraint rules
  and intent
• Bi-directional communication between design and
  manufacturing
• BOMs, parts availability and manufacturability

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Example - Choosing the Right ComponentSimple
Decision, Global Consequences
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Product Costs Committed Early
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Choosing the Wrong Component Can be a Disaster

• Cost
• E.g., consumer product designer picks very
  expensive part
• Not discovered until purchase requisition issued
• Either redesign or non-competitive price product
• Availability
• E.g., designer chooses perfect part
• Manufacturer gets BOM and can not get part in
  volume
• Either redesign or lag in volume production
• Manufacturability
• E.g., designer chooses good part for design
• However, part requires specialized manufacturing
• Either redesign or increase in manufacturing costs

?
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EDA Tool Integration Required with Corporate PLM
Systems and the Industry Supply Chain
Enterprise Integration
EDA Tools
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EDA Tool to Corp. Infrastructure IntegrationDMS
Reduces Design Time Product Cost

• Complete part information available
• Cost
• Availability
• Value
• Characteristics
• The right choice early in the process

• Design/part Information
• Availability
• Cost
• Manufacturability

Component Data
BOMs
Designer
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Technology ChallengesThe Ripple Effect of
Advancing Technology

• MHZ and GHz speeds
• 1500 to 3000 pins/package
• More FPGAs on PCB
• Electro-magnetic interference

Advances in IC/FPGA

• HDI/Microvia
• Embedded Components
• MCM
• Lead-free
• High-speed Materials
• Optical

Advances in PCB Fabrication
Advances in EDA Tools
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The Need for Speed
Clk to Q
Setup/Hold
Trace Delay
Margin
Timing Budget (ns)
300
100
Clock Speed (MHz)
30
10
0
20
40
60
80
100
Exponentially increasing clock speeds
Exponentially decreasing timing margins
The SERDES Design Trend
Faster rise times signal integrity issues
Optical Interconnects
15 10 5 1
gt12 Gbps Copper Signaling Limits
10 GbE
InfiniBand
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SerialRIO
FibreChannel
PCIExpress
SATA
GbE
1Gbps Parallel Bus Limit
Signaling Rate (Gbps)
HyperTransport
PL4
PCI-X
PCI
UP TO 66 MHz
AGPx
RapidIO
8.33 MHz
ISA
80s
90s
00s
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Multi-Gigabit Design Issues

• Require a whole new analysis and verification
  approach, including analysis of ...
• Loss and rise-time degradation
• Jitter
• Crosstalk
• Complex via effects
• Pre-emphasis/Equalization
• Differential path matching

Lossless
20 inches
40 inches
30 inches
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Integrated Systems Design

• High-end FPGAs are now commonplace on most PCB
  designs
• Implementing these on a PCB presents many
  challenges
• Timing closure on both the FPGA and PCB
• System performance optimization
• Reduction of design cycle time concurrent
  design
• Reduction of PCB layout time and manufacturing
  costs
• Use of advanced high speed (classic and SERDES)
• Use of advanced PCB fabrication technologies
• Mentor has addressed these challenges with our
  Integrated Systems Design (ISD) solutions and
  Partnerships with leading FPGA suppliers

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Expedition Enterprise Flow
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Expedition EnterpriseAddressing the Challenges
of the Global Enterprise

• Challenges of product design within a global
  enterprise
• Design team collaboration
• Intellectual property management
• Corporate enterprise integration
• Integrated system design
• Government regulation compliance

• Expedition Enterprise enables design teams to
  leverage the power of their enterprise
  environment to reduce product cost and design
  cycle times

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