Design and Implementation of VLSI Systems

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Design and Implementation of VLSI
Systems (EN0160) Lecture 30 Design Methodologies
using Tanner Tools
Prof. Sherief Reda Division of Engineering, Brown
University Spring 2007
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Modification to your standard cell library

• Added Abut frame/ports
• Added 3 more cells for P R flow
• Consistent I/O naming
• (No AOI21 and LAT should not be used)

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A symbol library in S-Edit has been prepared

• S-Edit is a schematic capture tool
• The symbols for the cells in S-Edit match those
  of L-Edit with the same input/output pad naming

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Start a new design
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Add a library (SCMOS) to your design
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The library content (cells show up)
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Add a view to your design
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You can draw your circuit in the view
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How can we add components to the view?
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You can create busses (bundles)
Wire (net)
Wire (net) label
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Then label the individual wires
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Repeat for other signals. Make sure to label the
input/output pads correctly
Check your schematic
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Export your netlist
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TPR format
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Switch to L-Edit
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P R setup
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Then P R
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Everything gets done for you!
Where are the pins?
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Make things easier by specifying pin locations
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Redo P R ? the IO pads to the boundary
You can extract to SPICE and continue as usual
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Hierarchical design in S-Edit
Create a symbol out of your register schematic
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Now create a new cell in your design (slide 5)
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Start adding your registers as instances
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Then interconnect your placed components
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A 8x8 tri-state bus enabler
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Now integrate into the RF
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Now P R the whole thing
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Turn on Metal 3 routing
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Overall flow
design entry
Schematic capture using S-Edit
IC layout/ area
P R using L-Edit
Cell library
SPICE
Verification timing/ power