SARA Scaleable Architecture for Realtime Applications

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SARA - Scaleable Architecture for Realtime
Applications -

• llh_at_idt.mdh.se

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CAL Personal

• Industrial Ph.D. students
• Stefan Sjöholm, (50, ABB ISY)
• Anders Rosvall (20, ABB CRC)
• Ashraf Fawzi (20, ABB NET)
• Research Fellow
• Vincent (Stanford,USA) 98, 3 weeks
• Vacant
• Research Engineer
• Tommy Klevin
• Industrial Partners
• XILINX, ABB Robotics, MENTOR/Microtec
• Perhaps Enea, Ericsson

• Scientific Leader/Senior Researchers
• (Research leader) Associate professor Lennart
  Lindh
• Professor Harald Lawsson
• Associate Professor Kuchcinski
• Ph.D. students
• Johan Stärner (Adj)
• Johan Furunäs
• Joakim Adomat (Adj)
• Mohammed El Shobaki
• Filip Sebek
• 2Vacant

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Research History 10 years
Power PC60K FPGAIndustry Ph.D
Hardware with VHDL Design and ASIC Tools
number of persons
RTU for Multiprocessor System
7
5
FASTHARDSingle Processor
4
FASTCHART Single Processor
3
2
1
1989
1996 1998
People
Industrial projects
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FASTCHART

• FASTCHART is deterministic with respect to
• Execution of CPU instructions,
• Execution of the real time operating system
  service.

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FASTCHART
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FASTCHART - CPU

• No IRQ
• Instruction 1-2 CPU cycle
• 36 instructions

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FASTCHART - RTK
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FASTHARD
9
FASTHARD
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RTU - Real Time Unit
Multiprocessor Kernel
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Yesterday, Today and Tomorrow
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SARA next generation-Scaleable Architecture for
Real-time Applications-

• The research question is will it be possible to
  meet the following objectives if software
  functions and new functions implements in
  hardware?
• Scaleable and Simpler
• Flexible
• Observable and Controllable
• Efficiency and higher Performance
• Better Low-Cost/Real-time Performance Value,
• Fault Tolerance,

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We work only with MIMD architecture
We work also with Power PC, VME, PCI bus ....
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Scalability and Simple
RAM
RAM
RAM
RAM
CPU1
CPU2
CPU0
CPUA
GRAM
RTUA
More performance - no change in software - more
processors
RAM
RAM
RAM
CPU1
CPU2
CPU0
Next sub system
RTUB
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Flexibility
Different software architectures could use the
same hardware architecture.
New version - no change in hardware - flexible
hardware
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Observable and controllable,
Shared Pool of Computer Resources...
Important, Important... the key to faster
verification and better analyse of RT-system
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Observable and controllable Road Map for ASIC
Design
gates pro week
ASIC
?
Verification
Design
1990
1995
2000
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Efficiency and Higher Performance

• Low Hardware and Software Overhead
  (simplifications),
• state-of-the-art high performance commercial
  standard microprocessors, buses etc.
• Hardware faster then software

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Cost/realtime performance,

• ASIC designs
• Standard Components, IP etc.
• Standard Software and debuggers
• System on Chip
• ......

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Fault tolerance,

• Better Task Memory Manager
• Better Watchdog functions
• Better Scheduling algoritms
• etc.

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SARA 98
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SARA 98- status today -
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Conclusion and future work