Exploiting Symmetry in SATBased Boolean Matching for Heterogeneous FPGA Technology Mapping

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Exploiting Symmetry in SAT-Based Boolean
Matching for Heterogeneous FPGA Technology Mapping

• Yu Hu1, Victor Shih2, Rupak Majumdar2 and Lei He1
• 1Electrical Engineering Dept., UCLA
• 2Computer Science Dept., UCLA
• Presented by Yu Hu
• Address comments to lhe_at_ee.ucla.edu

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Outline

• Background and Motivations
• Review of Standard SAT-based Boolean Matching
• Proposed Improvements
• Experimental Results
• Conclusion and Future Work

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Background

• FPGA technology mapping
• Map a design into a network of Programmable
  Logic Blocks (PLBs)
• Optimize for area, speed and/or power
• PLB containing heterogeneous devices requires
  Boolean matching (BM) to determine whether
  function fcan be implemented by hardware
  component H

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Example Boolean Matching (BM) for PLB

• Answer a Yes-No question
• Can a Boolean function f be implemented in PLB p?
• If yes, give the configuration bits of LUTs.

f1 (e c d b)a i.e., f1 za z e c
d b
f1 ea ca da ba f2 a b c d e
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Motivation for SAT Based PLB BM

• Application of FPGA PLB Boolean matching
• Technology mapping
• Re-synthesis
• Existing BM algorithms
• Decomposition based BM is lack of flexibility,
  i.e., algorithm is only applicable to selected
  BLE structure Cong, TCAD01
• BDD based BM is not scalable (memory explosion)
  Ciric, TCAD03
• Fast BM is hard to deal with programmable devices
  Wei, ISQED06
• SAT based BM Ling, DAC05Safarpour,
  DAC06Cong, FPGA07
• Introduces extreme flexibility
• Provide a tradeoff between memory and runtime to
  deal with complicated BLE structures
• Still slow, hard to be applied to complex PLBs

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Review SAT Based Encoding for BM

• Encoding non-programmable devices
• Requires common/interconnect variables
• Is a linear time procedure
• Example

f AND (x2z1) (x1z1) (x2x1 z1)
f OR (x3g) (z1g) (x3z1 g)
f total fAND fOR (x2z1) (x1z1) (x2x1
z1) (x3g) (z1g) (x3z1 g)
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Review SAT Based Encoding for BM

• Encoding programmable devices
• Configuration bits are encoded

f LUT ( x1 x2 L0 z1) ( x1 x2
L0 z1) ( x1 x2 L1 z1) ( x1
x2 L1 z1) ( x1 x2 L2 z1) ( x1
x2 L2 z1) ( x1 x2 L3 z1) ( x1
x2 L3 z1)
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Review SAT Based Encoding for BM
Configuration bits are encoded as SAT literals
G AND2 ( x3 f ) ( x3 f ) ( x3 z f )
G LUT2 ( x1 x2 L0 z) ( x1 x2
L0 z) ( x1 x2 L1 z) ( x1
x2 L1 z) ( x1 x2 L2 z) ( x1
x2 L2 z) ( x1 x2 L3 z) ( x1
x2 L3 z)
The solution of this SAT problem corresponds to
the Boolean matching results
G G AND2 G LUT2
SAT G expand GX/000, f/0 , z/z0 GX/001,
f/0, z/z1 GX/010, f/1 , z/z2 GX/011,
f/0 , z/z3 GX/100, f/1 , z/z4 GX/101,
f/1 , z/z5 GX/110, f/1 , z/z6 GX/111,
f/1 , z/z7
Boolean function
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Handle Input Permutation and Bridge
Virtual MUXes increase runtime exponentially!
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Impact of Virtual MUXes
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Symmetries in Circuits and PLB

• Functional Symmetries
• Variable a and variable b are symmetric if
  swapping a and b does not change the truth table
  of function F(,a,,b,)
• General symmetries which consider the permutation
  of more than two variables can also be explored
• Eg F(a,b,c) a(bc), where b and c are
  symmetric
• Architectural Symmetries
• Structures of certain inputs of a PLB are
  equivalent
• Eg Inputs of the primary input LUTs of each PLB
  are symmetric
• F(a, b, c, d)

F(b, a, c, d)
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Impact of Considering Symmetries

• The number of distinct permutations under
  symmetries decreases substantially
• Functional symmetries and architecture symmetries
  independently reduce 100x permutations

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Overall Algorithm
Boolean function
Target architecture
Functional symmetry detection
Pre-calculate architecture symmetries patterns
Pruning by architecture symmetries
Architecture symmetry information
Non-redundant permutation set (NPS)
Generate characteristic function template
Is NPs empty?
Characteristic function template
Y
N
Pop a permutation p
Exit
Pre-process for the target PLB, one-time cost
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Overall Algorithm (cont.)
Is NPs empty?
Target architecture
Y
N
Pre-calculate architecture symmetries patterns
Pop a permutation p
Architecture symmetry information
Replicate CNFs of p
Solve the SAT problem
Generate characteristic function template
N
SAT?
Characteristic function template
Y
Return implementable
Exit
Pre-process for the target PLB, one-time cost
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Experimental Results

• Experimental settings
• Tested by Boolean functions in MCNC circuits
• Target PLB is PLB_d
• Use minSAT1.14 to solve SAT instances
• Obtain over 100x speedup compared to the standard
  approach Ling05

Breakdown of speedup techniques
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Conclusions and Future Work

• An improvement for SAT-based Boolean matching is
  presented by considering functional and
  architectural symmetries
• Over 100x speedup is obtained compared to the
  standard SAT-based Boolean matching approach
• Future Work
• Integrate the improved SAT-based Boolean matcher
  into heterogeneous FPGA technology mapping phase
• Perform architecture exploration by our improved
  technology mapper

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Thank You!

• Exploiting Symmetry in SAT-Based Boolean
  Matching for Heterogeneous FPGA Technology
  Mapping
• Yu Hu, Victor Shih, Rupak Majumdar and Lei He