FED Status

1
FED Status
CCLRC, Rutherford Appleton Laboratory, Oxon,
UK Imperial College, London, UK Brunel
University, London, UK presented by John
Coughlan RAL
2
FEDv1 Summary
17 FEDv1 boards manufactured 6 commissioned at
RAL and delivered to CERN (4 used in Beam
Tests) 5 working boards kept at RAL IC for
verification of design. 6 boards from batch with
manufacturing failures on BGAs. Have some limited
test uses.
3
FEDv1 Design Testing

• Hardware
• Temperatures on FED. Resolved.
• FED power requirements finalised. Standard LHC
  crates satisfactory.
• Observation of FPGA loading problems. Rare. Temp
  dependence? Possible solution being tested.
• Firmware
• Baseline design working in Test Beams.
• Some readout errors in ZS mode. Under
  investigation.
• Further List of Improvements in URD 0.56.
• Prioritize. Concentrating on issues from Test
  beam.
• Software
• Test bench Framework released (production tests).

4
Temperature Measurements
Greg Iles Imperial College
Simple air deflector cures temperature problems
top
fans
top
bottom
5
FEDv2 pre-Production Board

• Minimal Hardware changes from FEDv1
• Power Block General improvements. FET
  controller.
• QDR Memory Replacement part (pin compatible)
  identified.
• (post fitted samples on FEDv1. An error seen but
  lacking Bscan file to verify BGA rework)
• FE FPGA Use larger 2M gate (pin compatible)
  part.
• ADC AD9218 Device Bug. Reduce gain by half.
  Simple mod.
• FPGA Configuration VME Boot device reprogram
  via JTAG cable.
• S-LINK TCS Signals New 6U VME Transition
  Card.
• TTCrx Intermittent problems are now understood.
  Simple fix.

FEDv2 design fixed. 2 boards now in manufacture.
Expected back in first half August. Plan to make
a further 20 before end of 2004 for Full Crate
tests. All parts except QDRs in hand.
6
S-LINK VME Transition Card

• Simple 6U board
• Provides interface between FED and Slink
  Transmitter
• Provides access to FED Throttle signals

James Leaver Imperial College
VME Backplane
Slink Transition Card
FED
Slink Data Control Signals
DAQ Slink Transmitter
6U
FED Throttle Signals
Ethernet Connector
3 Transition Cards out to manufacture by end
July. Expected back for test in
September. (compatible with both FEDv1 and FEDv2)
7
FED Schedule
8
FED Medium Term Production Plans

• Production Plans
• Q1/2004 Finalise design changes for FEDv2.
  Done.
• Sign off against FED User Requirements Document.
  Done.
• Q2/2004 Implement changes FEDv2 and review.
  Done.
• Q3/2004 Manufacture couple of FEDv2s. In
  progress.
• Q4/2004 Test FEDv2. Manufacture further 20
  FEDv2s.
• Parts for 30 FEDv2 now in hand or on order.
• RAL EU Tender for PCB
• Q1/2004 Place OJEC advert, invite EoI. Done.
• Q3/2004 Dispatch calls for FED Quotes. Identify
  2-3 companies. In progress.
• Q4/2004 Chose company. Detailed negotiations re
  Testing, delivery schedulesetc
• Q1/2005 Award contract.

9
Production Testing at Assembly
Testing by Assembly plant operatives
0. Quality Controls
during Assembly
process
BScan Testing (Ivan Church)
AOI, X-ray
1. Custom Tests at
Assembly Plant
BScan, VME crate
2. Tests at RAL
IC
OptoRx, Full crate
Test Bench for VME Testing (Matt Noy)
3. Tests at CERN
Prevessin
Readout Integration
4. Installation at CMS
USC55
10
Summary

• Prototype FEDv1
• Commissioning tests at (RAL, Imperial CERN)
  continuing well.
• Temperature issue resolved.
• Baseline Firmware design operational. (long) List
  of improvements to prioritize.
• Pre-production FEDv2
• Design fixed.
• 2 FEDv2 boards now in manufacture. Back August.
• Prototype S-LINK 6U Transition card in
  manufacture. Back September.
• Tender for PCB manufacture
• Using RAL EU Framework Tender to identify
  candidate companies.
• 2nd stage call for Quotes starts this month.
• Test Specification and Test bench s/w in progress.

11
End
Intentionally left blank
12
EU Tender Process

• EU Procurement Directives
• Goods Services gt 150 K
• Open Procedure Any party can tender, suitable
  for off the shelf items (e.g. components)
• Restricted Procedure Only N selected parties
  are invited to tender. N to be specified in
  advance. Two part process. Market survey
  Tender.
• Publish OJEC Notice for Expressions of Interest.
  Can pre-notify selected companies.
• Associated Questionnaire. Rather general
  document. Elicit size, history of company,
  financial standing, standards adherence,
  facilities etc.
• Evaluation and Selection of N companies to
  tender. Detailed enquiries. Visits.
• Issue Tender. Detailed specification.
• Still learning about these procedures. And how
  they fit with CERN (and CMS) procedures.
• RAL is just about to issue a general PCB
  manufacture notice. Plan to use FED as example
  for tender exercise.
• Some issues to decide, e.g. is separate tender
  for FPGAs necessary?

13
Restricted Procedure
14
Spares

• Manufacture all in one go.
• Need 440 for CMS Tracker.
• 60 working spares (for lifetime of CMS).
  Guesstimate.
• Assume final 500 delivered passing all
  commissioning tests.
• Issues for later productions.
• Component availability. Memories.
• Expert availability. Design and Test.
• Changes in pcb and assembly processes. Standards.
  Markets.
• Pb Free Directive
• Failure rates
• Hard to determine yet.
• Based on previous experiments assume normal
  failure rate is low after commissioning, bath tub
  distribution (excl catastrophic crate loss?).
• Consider accelerated ageing tests offered by
  assembly companies?
• Assume most failures can be repaired.
• OptoRx can be removed.

15
First FED Prototype (Jan 2003)
JTAG Boundary Scan
OptoRx
VME64x 9U board
CFlash
34 x FPGAs 40K-2M gates
96 channels
Event Buffers
Analogue
Power
TTC
Deliver FED Package Hardware Firmware Softwa
re
Primary Side (Secondary side has 1/2 analogue)
16
First Fully Assembled Board
Secondary Side
Primary Side
FE Unit
9U VME64x
BGAs 676 pins _at_ 1 mm pitch
PCB (2mm) 14 layers (incl 6 power ground)
Test with JTAG Boundary Scan
6 K components (smallest 0402) 25 K tracks
96 ADC channels AD9218 Dual package 10 bit _at_ 40
MHz
1/2 Analogue circuitry on Secondary Side
Highest density at Front-End Units
17
CMS Tracker FED Firmware Status
14th July 2003
System ACE
EPROM
VME FPGA
Ed
DAC
EPROM
Opto Rx
Temp
System ACE
ADC
DAC
VME Bus
Opto Rx
Temp
VME
ADC
Temp
I2C
Clocks
Serial Controls
Regs
Clocks
Serial Comms
Regs
Serial Controls
VME LINK
Input
Data
Data
Header Mode
Scope Mode
Frame-Findng Mode
Input
Ed
FIFOs
Output
DELAY FPGA x 3 x 8
BE FPGA
Saeed
Scope Mode
Cluster Finding Mode
Serial Comms
VME Link
Regs
External Devices
FE FPGA x 8
Ivan
To be Implemented
S-LINK
S-LINK
Control
Clocks
Headers
Under Simulation
Throttle
TCS
Input
Under Test on FED
QDR Write
QDR Read
TTC chanA
TTCrx
Data Readout
Saeed, Ivan
Working on FED
Chan B
QDR
Controls
Ed, John
QDR
Only for FEDv2
18
FEDv1 Firmware
15th March 2004
System ACE
EPROM
VME FPGA
Ed-gtSaeed
DAC
EPROM
Opto Rx
Temp
System ACE
ADC
DAC
VME Bus
Opto Rx
Temp
VME
ADC
Clocks
I2C
Clocks
Serial Comms
Regs
Clocks
Serial Comms
Regs
Data
Serial Comms
VME LINK
Input
Spy
Data
Header Mode
Header Mode
Cluster Mode
Input
Ed-gtSaeed
FIFOs
Scope Mode
Output
DELAY FPGA x 3 x 8
BE FPGA
Saeed
Scope Mode
Serial Comms
VME Link
Regs
External Devices
FE FPGA x 8
Saeed
To be Implemented
S-LINK
S-LINK
Control
Headers
Under Simulation
Throttle
TCS
Input
Under Test on FED
QDR Write
QDR Read
TTC chanA
TTCrx
Data Readout
Saeed, Ivan
Working on FED
Chan B
QDRs
Controls
Ed, John
FEDv2
19
Temperature Testing (Greg Iles)

• Will components on FED exceed operating
  temperature in CMS?
• Analogue OptoRx lt 70C
• Differential Buffer lt 85C
• ADC lt 85C
• Need to emulate conditions we will have in CMS
• LHC crate. All measurements adjusted for intake
  air at 18C.
• 3 FEDs placed next to each other in crate. The 2
  external FEDs restrict airflow and mimic to some
  extent heating from crate of FEDs
• 1 FT Ensemble used to drive all FED channels with
  100kHz frames.

20
Power
...plus Transition cards CC