Whatever their origin, all devices share the same Achilles' heel: the battery'

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Whatever their origin, all devices share the
same Achilles' heel the battery.

• Power Management
• By
• Sameera.P

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Agenda

• Motivation
• Power Management Techniques
• Thrifty Barrier
• Function Level Power Estimation
• Dynamic Power Management
• Summary
• References

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Motivation

• Power management for computer systems are
  desired for many reasons, particularly
• For portable and embedded systems to prolong
  battery life and reduce heat dissipation.
• For desktop systems reduce cooling requirement
  and reduce noise.
• For supercomputers reduce operating costs from
  energy and cooling.
• Lower power consumption also means low heat
  dissipation, which increases system stability,
  and less energy use, which saves money and
  reduces the burden on the environment.

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Processor Level Techniques

• The power management for microprocessors could be
  done over the whole processors or some fine-grain
  areas.
• For global power control, there are
• Dynamic Voltage and Frequency Scaling (DVFS an
  energy-saving technique that consists of varying
  the frequency and voltage of a microprocessor in
  real time according to processing needs.
• Intel SpeedStep, AMD Cool'n'Quiet, AMD PowerNow!,
  VIA PowerSaver allows the clock speed of a
  processor to be dynamically changed depending on
  workload levels

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For information

• The power breakdown for a laptop computer
• VLSI digital components 21
• Display 36
• Hard drive 18
• and wireless LAN 18

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Power Management Techniques

• Thrifty Barrier SMPs
• Dynamic Power Management
• Function Level Power Estimation

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Thrifty Barrier Energy Aware Synchronization in
SMPs

• Past research on power aware systems mostly
  focuses on uniprocessors
• The most energy-efficient execution in each
  processor may not translate into most efficient
  overall execution
• There are issues unique to multiprocessors that
  warrant investigation

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Parallel Workload

• In a parallel workload, the overall performance
  depends on all the threads
• Critical path may depend only on a few threads
• Source of energy waste unique to parallel
  systems Energy waste in Barrier synchronization

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Barrier-synchronized Parallel Codes

• Threads often spin-wait at barriers for all the
  threads before moving to a different phase of the
  computation
• Traditional low-power techniques for uni
  processors are unfit for multithreaded scenario

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Thrifty Barrier

• Estimates the wait time and forces the processor
  into an appropriate low-power sleep state
• Many commercial processors offer various such
  sleep states
• The thrifty barrier also strives to wake up the
  processor just in time to avoid potential
  performance degradation

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Thrifty Barrier Key Challenge

• Accurate estimation of barrier stall time for
  each barrier instance
• It allows judicious selection of the
• Right low power state to maximize energy savings
• Bring processor back to minimize performance
  degradation

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Conventional Barrier

• Barrier Spin loop is highly inefficient
• Only the last iteration is productive
• All the spin energy is wasted in unproductive
  consumption

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Thrifty Barrier
Save the energy that would be wasted in the spin
loop Transitioning requires non-negligible amount
of time
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To add

• Thrifty barrier is a modest combination of
  hardware and software
• Barrier is augmented with a simple prediction
  code to decide the low power state
• The Aim

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Function Level Power Estimation

• To predict the power dissipation of embedded
  software
• Models at software level are difficult to build
  because of the great variety and complexity
• Instruction level power model was proposed

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• Each instruction and instruction pair are
  assigned a fixed energy cost.
• Power Data Bank
• Power Estimation Technique is built on the above
  model
• Makes use of profiling and tracing tools

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Power Formulation
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• Vendors can packet the power data bank with
  their microprocessor and provide users the
  ability to conduct power estimation
• Users are assured of the high accuracy caused due
  to function-level model

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Dynamic Power Management

• Flexible and general design methodology
• Aims to control performance and power levels
• Power Manager
• Power Management Policy
• The problem in DPM is the changing power state
  penalty

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• Non ideal DPM wastes the idle interval at the
  second idle period and pays a performance penalty
  at the third idle period.
• Inefficiencies come from the inaccurate
• prediction of the duration of the idle period
  or, equivalently, the arrival time of the next
  request for an idle component.

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Summary

• Power is one of the concerns when user select
  hardware to perform their programs
• The barrier construct used in parallel
  programming can be used to find idleness
• Power consumed during memory accesses accounts
  for a significant percentage of the total power
  consumption

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References

• Function-level power estimation methodology for
  microprocessors.Gang Qu, N. Kawabe, K. Usarni,
  and M. Potkonjak.
• Dynamic Power Management for Nonstationary
  Service Requests Eui-Young Chung, Luca Benini,
  Alessandro Bogliolo,Yung-Hsiang Lu, and Giovanni
  De Micheli, Fellow, IEEE
• The thrifty barrier Energy-aware synchronization
  in shared-memory multiprocessors Jian Li, Jose F.
  Martinez, and Michael C. Huang
• Analysis of power consumption in memory
  hierarchies Patrick Hicks, Matthew Walnock, and
  Robert Michael Owens.

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• Exploiting Barriers to Optimize Power Consumption
  Chun Liu Anand Sivasubramaniam Mahmut Kandemir
  Mary Jane Irwin
• Hierarchical Adaptive Dynamic Power Management
  Zhiyuan Ren