Introduction to Pipelining

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• Introduction to Pipelining

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A Motivating Example
Do Laundry
Wash Dry Fold Put Away
Total time 2 hours
Assumption we can break up Do Laundry into
four steps, all of which take 30 minutes to
complete.
Wash
Dry
Put Away
Fold
30mins
30mins
30mins
30mins
Wash
Dry
Put Away
Fold
Wash
Dry
Fold
Wash
Dry
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Pipelining Your Laundry
Note total time is now 3h 30mins.
Note it still takes me 2 hours to complete one
load.
Note after the 2nd hour, I finish one load every
30 mins.
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Performance with Pipelining
The gains with pipelining come from throughput
not from reducing the execution time of an
individual instruction.
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Comparison
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MIPS Instruction Execution Sequence
We can break down the execution of each
instruction into a sequence of five different
steps
1. Fetch instruction from memory.
2. Read registers and decode instruction.
3. Execute operation or calculate an address.
4. Access an operand in data memory.
5. Write the result into a register.
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Timing for each instruction execution step
Question If we want to build a pipelined CPU for
MIPS, how will we deal with the fact that the
total execution time varies according to the kind
of instruction?
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What you could have guessed by now MIPS was
designed for pipelining

• All instructions are the same length.
• Operands are always aligned in memory.
• Few instruction formats.
• Few addressing modes (memory operands appear
  only in load and store instructions).

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Adapting the Single-cycle Datapath for Pipelining
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Executing Instructions with Pipelining
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More Registers
Pipeline registers Intermediate storage
Question How does one determine the length of
these registers?
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Pipelining Hazards
What if the next instruction cannot execute in
the following clock cycle?
Structural hazard Bad hardware support. We
cant execute a combo of instructions in the
same clock cycle. Example memory. Solution
stall, design.
Control hazard The result of one instruction
determines what happens to other instructions..
Example branch. Solutions stall, reorder,
predict.
Data hazard An instruction depends on the
result result of a previous instruction that is
still in the pipeline.. Example add s0,
t0, t1 sub t2, s0, t3 Solution
stall, reorder, forwarding (or bypassing).
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Structural Hazard

• What if we had a single memory

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Data Hazard
add s0, t0, t1
sub t2, s0, t3
Reordering
add s0, t0, t1 sub t2, s0, t3 addi t4,
t4, 32 sll t5, t5, 5
add s0, t0, t1 addi t4, t4, 32 sub t2,
s0, t3 sll t5, t5, 5
add s0, t0, t1 addi t4, t4, 32 sll t5,
t5, 5 sub t2, s0, t3
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Data Hazard
add s0, t0, t1
sub t2, s0, t3
Forwarding
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Forwarding is not a Panacea
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Control Hazard
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Branch Prediction

• Assumption Most of the time the branch is not
  taken.

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Execution of a lw
Instruction Fetch
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Execution of a lw
Instruction Decode
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Execution of a lw
Instruction Execution
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Execution of a lw
Memory Access
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Execution of a lw
Write Back to Register
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Correction to the Datapath
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Pipelined Control
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Points to Notice

• Theres no need to have write controls to the PC
  or to the pipeline
• registers.
• Fetch nothing to control. Same thing done every
  clock cycle.
• Decode nothing to control. Same thing done every
  clock cycle.
• Execution decide how to use the ALU (operands,
  operation, result)
• RegDst, ALUOp, ALU Src.
• Memory access branch, load and store
  instructions have different
• requirements, so one must specify Branch,
  MemRead, MemWrite
• Write back choose what gets written back to the
  register file (the ALU
• result or a memory value) the controls are
  MemToReg and RegWrite.
• We use the same control lines as before, but
  group them by pipeline stage.

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What has Really Changed
Remember Each instruction defines what control
values are applied.
Question What happens now that I can have up to
5 instructions executing at the same time in the
datapath?
All control decisions are made during the
instruction decoding and are carried forward
across stages in the pipeline.
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Pipelined Datapath and Control