Jan M' Rabaey

1

• Jan M. Rabaey
• EECS Dept.
• Univ. of California, Berkeley

2
PicoRadios
Ubiquitous Sensor and Monitor Networks

• Meso-scale low-cost radios for ubiquitous
  wireless data acquisition that
• are fully integrated
• Size smaller than 1 cm3
• minimize power/energy dissipation
• Limiting power dissipation to 100 mW
  enables energy scavenging
• and form self-configuring ad-hoc networks
  containing 100s to 1000s of nodes

3
A truly ubiquitous testbed Piconode I

• More than 60 nodes operational
• Being used in wide variety of
• experiments especially on ad-hoc multihop
  networking

4
Manufacturing of Wireless System Casings
Dan Odell
Components from both the electrical and
mechanical domains are assembled into the
completed product. Domain couplings are
addressed by the design specifications, providing
for a smooth integration between the subsystems.
Injection Molding tooling is generated, allowing
high quality casings to be rapidly produced.
Casings must be specifically designed to
accommodate this process.
5
An Experiment in Ad-hoc Networking
Jonathan Reason, Fred Burghardt, Ruth Wang, Hugo
Hsi, Howard Tsai
Sensoring Application
Queries
Network Layer
neighbors
Link level reliability
Traffic density
Data Link Layer
of channels available
Modulation
Radio Data Rate
Physical Layer
Bluetooth Radio
6
Ad-hoc Multi-Hop Networking Testbed
Input Panel Creates network queries for specific
regions and types of data.
Neighborhoods

• Routing Map
• Green nodes generate requests
• Red nodes return data
• Routing can be multi-hop

7
Some new additions to PicoRadio Board Family

• Sensors
• 2-axis accelerometer
• 2-axis magnetometer
• Temperature
• GPS (not yet installed)

Magnetometers
Accelerometers
Temperature
GPS

• Working Applications
• Roll and pitch inclinometer
• Compass
• To be used as trip-wire in upcoming DARPA demo

Patch antenna board
8
Acoustic Anemometry
Initial results
Given ?f, and d, v can be calculated using
v 2? ?f (d/ ?? )
9
PicoNode V2 An Exercise in SOC Design
Methodology
Mika Kuulusa, M. Sheets, J. Ammer
PicoNode II (aka TCI) 1.2 Mbit/sec
Transceiver Supports 18x64kBits using TDMA
MAC All chips designed using rigoroustop-down
design flow.
Excellent news! Both chips seem to be fully
functional. More precise measurement data to
follow!
10
PicoNode IIIv1 (aka the Quark Chip Set)

• First Integrated PicoRadio for Wireless Sensor
  Networks
• Anticipated Power Dissipation (average) 1 mW
• Projected to be Operational by End of Year
• Combines the Following Components, Packaged
  together on a Single Substrate
• Digital Network Processor (charm quark)
• distributed sensoring application and limited
  sensor interface
• full ad-hoc and energy-efficient network protocol
  stack
• limited form of localization
• 10 kBit/sec peak On-Off keying wireless physical
  layer
• Anticipated size 4 mm x 4mm
• Aggressive use of power-down allows for standby
  power in the mW range
• Analog RF Front-end (strange quark)
• Uses on-off keying modulation scheme
• Supports 2 parallel 10kBit peak RX-TX RF channels
  (around 1. 9 GHz carrier)
• Simplified architecture using RF passive
  filtering avoids high frequency components
• Anticipated size 1mm x 1mm, Peak power 4 mW
  (Tx), 3mW (Rx)
• Miscellaneous components
• 4 FBAR resonators (2 per RF channel) (up and
  down quarks)
• Sensor

11
PN-IIIv1 Packaged (rendering)
3 x 5 cm2 solar array
Components and batterymounted on back
Dan
12
PicoNode III Architecture
Digital Network Processor
Flash Storage
16kB CODE
4kB XDATA
DW8051
256 DATA
Chip Supervisor
20MHz Clock Source
Serial
sfrbus or membus?
Solar Cell
MAC
SIF
FlashIF
Serial
ADC
Voltage Supply
GPIO
Voltage Supply
SIF
Voltage Supply
LocalHW
PHY
ADC
Sensor1
Sensor2
RF Transceiver
PrgThresh0
PrgThresh1
Tx0
Tx2
User Interface
OOK Receiver
OOK Transmitter
SIF sensor interface
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PN3 transceiver (strange)
Brian Otis, Richard Liu, Yuen-Hui, Ulrich Schuster

• physical air interface specifications
• 10kbps, Tsym 100µs
• On-off keying (OOK) modulation
• 2 FDD channels (traffic, broadcast)
• time-multiplexed rx/tx
• support carrier-sense
• OOK receiver
• 800 nsec power-up time (LNA, tx shutdown)
• control rx_in, rx_ena
• carrier sensing implementation
• Active power consumption 3mA _at_ 1V
• OOK transmitter
• 800 nsec powerup time (oscillator, PA, rx
  shutdown)
• control tx_out, a_ena
• Active power consumption 4mA _at_ 1V

OOK XCVR
tx_out0
tx_out1
a_ena0
a_ena1
rx_in0
rx_in1
rx_ena0
rx_ena1
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Transmitter
FBAR-based
15
A First Operational FBAR-basedLow-energy
Oscillator (test-chip)
300 mW 1.9 GHz Oscillatorwith low phase noise (lt
100 db at 10 KHz) Vdd 1V, Vswing
100mV Combining CMOS circuitry (0.18 mm
CMOS) with FBAR (using wire bonding)
Oscillator cycledon/off at 20 kHz rate
To be presented at 2002 ESSCIRC Conference
16
Receiver
Vdd
C
Ld
Vb1
Vb2

• Two Channel
• Channel Spacing 50MHz
• 10kbps/channel
• Issues include noise suppression and isolation
  between RF filters
• Prototype Target 3mA _at_ 1V

Vb3
Vrf
Lg
Lchoke
Matching
Ls
FBAR
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Freq Domain Illustration

Low Q Prefilter


High Q Channel

Select

Downconversion via Envelope detection

f
/2

f
/2

s
s
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Envelope Detector
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PN-v3 TX/RX Testchip
0.13 mm CMOS In fab as of 4/10/02
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Rx/TX (strange) Status

• First test-chip operational
• Second test chip submitted on April 10, 2002,
  containing all components of complete transceiver
  (oscillator, PA, oscillator PA, tuned LNA,
  envelope detector, LNA envelope detector)
• Complete RF transceiver to go into Fab at
  late-summer

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Digital Network Processor (Charm)
16kB CODE
4kB XDATA
DW8051 microcontroller
256 DATA
Chip Supervisor
Interface to external flash
Serial
Data and power networks
MAC
SIF
FlashIF
Serial
ADC
GPIO
SIF
LocalHW
PHY
ADC
2 8-bit sensor interfaces
Simple locationing based on hop-count
M. Sheets, Huifang Qin, Josie Ammer, Tufan
Karalar, Jie Zhou
22
PN IIII net/mac/phy
Chunlong Guo, Charlie Zhong, En-yi Lin, Mei Xu,
Jie Zhou, Rahul Shah
(standard cells)
(standard cells)
(DW8051)
1us
1ms
1s
MCU
ASIC
ASIC
OOK XCVR
Datalink
PHY
Network
Transceiver access control PPDU assembly Frame
synchronization (RX) Carrier sensing (TX) RSSI
measurements Channel monitoring Signal processing
Media access control MPDU assembly CRC check,
acks Initialization Neighbour table MPDU
buffering (rx/tx)
Packet assembly Localization control Packet
transmission Network flooding Routing tables
23
MAC Design Methodology
Mei Xu and Jie Zhou
System-level Verification Simulate for All
Scenarios Using Simulink
ASIC
24
Top-Level Block Diagram of Data Link Layer in
Simulink
Colors represent Power Domains
25
Pseudo-Asynchronous Wake-up
26
Positioning

• Hop Terrain Algorithm
• Count of hops from anchor nodes
• Triangulation using 3 anchor nodes
• No need for ranging
• Initialization flooding
• Maintenance periodic flooding

27
Reactive Behavior Diagram
Sensor/actuator interface
App/UI
User interface
Sensor/ actuators
Transport
Aggregation/ forwarding

• Blocks powered down by default to reduce
  leakage.
• Wake-up triggered by events (signals) from
  neighboring node, sensors, or chip supervisor.
• Chip supervisor chip OS. manages concurrency
  and time performs power management

Network
Locationing
Chip Supervisor
DLL (MAC)
Energy train
Baseband
Ranging
Reactive radio
RF (TX/RX)
Antenna
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PicoNode III chip level power control

• Functional unit power control
• Gated clocks and switchable power supplies 0,
  0.2, 1.0V
• All units except Timer-Subsystem powered down in
  standby
• System supervisor
• Microcoded state machine that executes only when
  a new event occurs
• Generates power control messages to functional
  units
• Timer subsystem
• Free-running system timewheel
• Allows other blocks to go to sleep and wake up
  with alarms (callbacks)
• Interfaces to supervisor as just another event
  source

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How to Deal with Memories in Standby?The
Dual-Voltage Scheme (Huifang Qin)
Vthp sVthg - sVthl Wp - sWg sWl Lp -
sLg - sWl
Vthp sVthg sVthl Wp - sWg - sWl Lp -
sLg sWl
Vthn sVthg sVthl Wn - sWg - sWl Ln -
sLg sWl
Vthn sVthg - sVthl Wn - sWg sWl Ln -
sLg - sWl
Experimental worst case parameter variation
scenario for SRAM data retention voltage DRV_wc
90 mV
Goal Reduce standby leakage
Preserve storage content Solution
Vdd_standby DRV_wc V_NM
90mV 110mV
200mV Simulation Results
Memory state preserved Leakage power
saving _at_ 10ms standby Pstandby 11 Pleak
Minimum standby time for power saving Tmin
73 us Wake Up Time 7ns (with 100um
wide PMOS power switches)
Memory State Preservation
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Memory Test Chip with SC Converter

• Switched-Capacitor Converter
• for Standby Supply Voltage Generation
• 1V gt 200mV
• 1.3uA gt 6.5uA
• Output Power 1.3uw
• Vout 190mv /- 3mv
• Efficiency
• 90 w/o clock power
• 80 w/ clock power

NMOS 0.75V/-0.25V PMOS 0.25V/-0.5V
M6 power loss

1.3 mm2 SRAM Leakage Control Test Chip (0.13um
Process, with 4K bytes SRAM embedded )
31
Digital Network Processor Status

• Complete Functional Description of Complete
  System Virtually Finished (combined C, Stateflow
  and Simulink)
• Version currently operational on PicoNode I
  testbed
• Module Design April 1 July 30
• Phy, MAC DL, Localizer processors (ASIC)
  (preliminary synthesis runs have been done and
  show minimal size requirements lt 1 mm2)
• DW8051 (first test generations have been done)
• Chip Supervisor power network
• Memory sub-system
• Chip Integration and Verification August
  September
• Chip tape-out October 15, 2002
• Expected chip-size 4 x 4 mm2

32
Energy Train
Shad Roundy, Sid Mal

• Solar cells chosen as energy source for PN3 v1
• Under reasonable light conditions (about 1
  mW/cm2 ? 15 cm2 array)
• Output voltage 1.2 V

Using commercial dc-dc converter
33
An Alternative (powered by vibration)
34
Optimized PiezoElectric Prototypes
Shad Roundy
35
Micro-machined Vibration Generators
SEM images of test device
Models of device in fabrication
240 teeth
10 mm spacing between teeth
36
Integrated System Design
Mike Montero, Shad Roundy, Paul Wright
As wireless systems become smaller and smaller,
new methods for packaging and system integration
will need to be developed. Cooperative effort
with Fraunhofer Berlin
Piezo Bender Powered System
Solar Powered Design
37
Summary PicoNode III

• Complete architecture of integrated piconode
  defined (lt 1 mW)
• All components for Piconode III v1 should be in
  fab by mid fall
• 2 custom processors 4 FBAR modules
• Off-the-shelf components (solar cells, battery,
  regulator, sensor, crystal oscillator, flash)
• Planning started on packaging options

38
Beyond PN III

• Extending the Lifetime of Sensor Networks
• Wake-up Radio
• Localization
• Design Methodology (with GSRC)
• Ambient Intelligence one of main GSRC drivers
• Bringing Power even Lower!
• Reliable computation on unreliable
  platformsComputation in the ultra low-voltage
  space

39
Lifetime of Sensor Networks

• How to mitigate hot-spots in sensor networks?
• Intelligent routing
• Data aggregation
• Distributed coding
• Topology planning
• Altruistic nodes
• Dynamic relocation of functionality

The hot-spot problem
Established strict upper-bounds on lifetime!
D. Petrovic, R. Shah, K. Ramchandran Proposal
submitted to NSF
40
Routing with Aggregation

• Implemented routing algorithm that allows packets
  to be aggregated reducing communication overhead
• 85 reduction in the amount of energy spent on
  transmitting packet headers in topology modeled
  on BWRC

Controller Sensors
41
Distributed Source Coding

• Developed correlation tracking algorithm to allow
  distributed source coding of correlated sensor
  readings
• 40 savings on energy used to transmit sensor
  readings

42
Design Methodology for Wireless Networks

• Network Platforms
• Inspired on Platform-based Design (GSRC)
• Direct result of GSRC- BWRC cooperation
• APIs sets of Communication Services
• Communication Refinement

Marco Sgroi, Rong Chen, ASV
43
Ulysses

• Protocol Synthesis from Scenario-based
  Specifications
• Avoid early partitioning into components
• Specify scenarios independently
• Compose scenarios
• Algorithm
• PNs Synthesis from MSCs
• Pattern-based Design
• Library of Protocol Patterns
• Application to Picoradio Protocol

read a
write b
44
Metropolis Metamodel Overview

• Metamodel
• Describe the behavior of a concurrent system
• Do not commit to any particular model of
  computation
• Handle both control- and data-intensive
  systems in a harmonious way

45
Picoradio Data-link Layer Modeled by Metamodel

• Objective
• Test metamodel in wireless sensor networks
  domain
• Help designers smooth design flow by using
  metamodel

46
PicoRadio in the News

• Presentation at ISSCC 2002 (Emerging technology
  session) for overflow crowd
• High Profile Article in MIT Review
• Profiled in Daily Californian TWO times (energy
  scavenging, picoradio networks) in last months!

MIT Review
47
Summary and Perspectives

• Major progress towards first ultra low-power
  PicoRadio incarnation
• Stayed tuned for next retreat
• Testbed in full operation
• Demonstrating concept of robust and scalable
  ad-hoc networking
• A number of exciting new technologies have
  emerged
• Starting reflections on What is next

48
RF MEMS/CMOS Co-Design

• Perform Frequency Discrimination Using Passive
  Structures (instead of oscillatormixer)
• Co-Optimize MEMS CMOS devices
• Ultimately Integratable with Silicon devices

Co
Lx
Cx
Rx