Low Power IP Design Methodology for Rapid Development of DSP Intensive SOC Platforms

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Low Power IP Design Methodology for Rapid
Development of DSP Intensive SOC Platforms
T. ArslanA.T. ErdoganS. MasupeC. Chun-FuD.
Thompson
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Contents

• Introduction to power consumption
• Introduction to Main Concepts
• Low Power Design Methodology
• IP implementations
• Results and conclusions

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Power Consumption in CMOS-Based DSP Systems
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Common Approaches to Low Power Design

• Supply Voltage Reduction
• Clock Gating
• Disadvantage
• Added design effort

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Systematic Low Power Design Approach

• Exploit Algorithmic Correlations and
  Redundancies within an algorithm, then Map to
  hardware.

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Systematic Design Implementation Framework
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Rapid Design and IP-Based Integration Platforms
IPx
WL
IP
N
. . .
. . .
Multiplier
Algorithm
IPy
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Developed IPs
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Parameterisation Options
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Design Flow for Filter IPs
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FIR Filter Implementation
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Typical Single Multiplier DSP Processor
Architecture
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Transpose Direct Form (TDF) FIR Structure
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Modified DSP Processor Architecture for TDF FIR
Filter Implementation
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An Example SFG for IP2
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Coefficient Memory Configuration with Coefficient
Ordering

• Order coefficients such that adjacent
  coefficients are highly correlated.

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• Coefficient Word
• SF Shift Flag
• SF 1 shift
• SF 0 no shift
• PCVMA Pre-Calculated Value Memory Address

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Coefficient Word Decomposition (Verilog Code)
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An Example SFG for IP3
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Memory Operations (Verilog Code)
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Software Implementation Example for IP3
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Power Evaluation
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Filter Specifications
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Power Reductions Achieved (wordlength 16 bit)
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An example of a 6-tap FIR filter with block size
of 3
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Power Reductions for IP4 (wordlength 16 bit)
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Reductions in Number of Memory Accesses ()
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Coefficient Segmentation Algorithm
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Example Segmentations
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Example Segmentations
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Coefficient Segmentation Algorithm for Twos
Complement Coding
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Coefficient Segmentation Algorithm for
Sign-Magnitude Coding
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Total switching activity of H and M coefficient
sets with Twos Complement Coding
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Total switching activity of H and M coefficient
sets with Sign-Magnitude Coding
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Simplified Filter Architecture for Mixed-Mode
Multiplication
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Simplified Filter Architecture for
Sign-Magnitude Multiplication
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Example Switching Activity Distribution with
Twos Complement Coding (N89, W16)
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Example Switching Activity Distribution with
Sign-Magnitude Coding (N89, W16)
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Power Reductions Achieved with Coefficient
Segmentation
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Power Reduction in Multiplier Circuit (wordlength
16 bit)
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47
44
53
62
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Power Reduction (wordlength 16 bit)
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Power Reduction at Coefficient Bus (wordlength
16 bit)
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37
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54
54
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DCT Implementation Scheme
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2-D DCT Implementation Approach
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Simplified Architecture of the DCT Processor
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Conventional Programmable FIR Filter Architecture
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TDF with Coefficient Ordering Programmable FIR
Filter Architecture
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Power Reduction ()
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Top View of IP1
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Block Report for IP1
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Top View of IP2
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Block Report for IP2
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Top View of IP3
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Block Report for IP3
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Area Comparison
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Top View of IP4
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Top View of IP5
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Top View of IP6
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Case Study a 34-tap bandpass filter
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Area and Power Characteristics for the Example
Filter
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Conclusions

• A methodology for Low Power Implementation of DSP
  functions has been presented.
• The methodology has been used to develop a number
  of IPs.
• Significant reductions in Power is reported.
• Power reduction is achieved in the multiplier and
  system buses.
• Methodology can be used for prototyping other DSP
  functions.