TRD Status Report

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Title: TRD Status Report

1
TRD Status Report
LHCC Comprehensive Review, 20-21 March 2006,
Johannes P. Wessels Univ. of Muenster
Project leader Johanna Stachel,
HeidelbergDeputy project leader Peter
Braun-Munzinger, GSITechnical Coordinator
Johannes P. Wessels, Münster

brief overview
chamber production
status
super module
insertion tests
design
integration of services
services

electronics
PASA - pre-amplifier
TRAP - digital chip
system integration MCM readout boards

detector control system
summary
milestones

2
Transition Radiation Detector (TRD)

Purpose
electron ID in central barrel pgt1 GeV/c
fast trigger for high momentum particles
Parameters
540 modules -gt 760m2 (50 funded)
length 7m
anticipated X/X0 15
28 m3 Xe/CO2 (8515)
1.2 million channels
Institutions
Athens, Bucharest, Darmstadt, JINR,
Frankfurt, GSI, PI Heidelberg, KIP Heidelberg,
Cologne, Karlsruhe, Kaiserslautern, Münster, Worms

3
Chamber Production

stable production at 4 sites (Bucharest, Dubna,
GSI, Heidelberg)
Frankfurt ramping up production - started in fall
2005
since decision for Layer 0 swift procurement and
production (completed for first super module)
noticed problem with insufficient surface
resistivity of AW106 glue after curing (large
dark current)traced back to change in the
manufacturing process of the gluecorrective
action additional cleaning step with ethanol
after curing

4
Leakage Current Path
backpanel
pad
anode plane
cathode plane
drift space
glue
TRD radiator
5
Surface Resistivity
Chr. Schmidt, GSI
6
ROC production status
C. Adler, Heidelberg
Status 25.2.06 Bucharest Dubna Frankfurt GSI Heidelberg Sum
taped 2 2 5 5 14
tested taped 2 13 2 17
glued (under testing) 1 2 1 2 6
tested glued 36 33 40 21 130
to be repaired 5 3 2 10
Sum 167(10) 62(66) of TRD
since Christmas 40 additional chambers
completed global production rate 6 chambers/week
7
TRD rail system in space frame

self-locking rail system installed, aligned
in SF
different types of rails depending on
position
clearances checked
final adjustment after SF installation in
magnet (April)

8
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9
Super Module Production Status
V. Chepurnov, JINR B. Windelband, HD, W.
Verhoeven, MS
-gt all pieces finished for first super module -gt
first assembly of super module mechanics
successful in February 06
10
First Super Module Assembly
11
Mounting L0 Chamber
12
Full Length Assembly
13
Super Module Service Sides
A-side
gas cooling
C-side
LV power detector control high voltage
readout fiberspre-trigger boxDCS power
14
Super Module Installation
15
SM and Manipulator
16
SM Insertion into Manipulator
Manipulator adaptedto final super
moduledimensions
Insertion test at CERN scheduled for April/May
06progress according to schedule
17
Bus Bar Layout
Chr. Lippmann, GSI K. Oyama, HD

capacitors added
design successfully tested
producer identified
order for first 2 SM placed

18
Cooling
A. Marin, GSI B. Windelband, HD

65x10x2mm manifolds under construction for first
layers
directly mounted on bus bars
delivery of all pipes for 50 TRD, 65x8x1mm end
of April

cooling plant construction well under way
commissioning will follow installation of first
super module(September)

Cooling pipes
19
Layout of cooling meanders
N. Heine, MS A. Marin, GSI
readout chamber
readout board
cooling pathon MCMs maximized 90mm
DCS
ORI
detectorcontrolsystem
optical readoutinterface
20
Production of cooling meanders

thermal contact epoxy loaded with Al powder
(plate-meander)
Thermaglue - heat conducting silicone between
plate and MCM
tools ready for production (8/RoB)
material in hand for 1st super module
20 of meanders finished
manufacturer identified
material on order for 50 TRD

21
Temperature Distributions
?T20 K
temperature profile for differentload
conditions on 2 ROBs all sensors exhibit
similarprofile
22
Gas System
C. Garabatos GSI R. Stadler, HD

production and commissioning schedule fixed with
gas working group (contingent on delays in other
systems)
on-detector pipe layout finalized
small reliable bubbler designed and tested
Sep/Oct 06 - commissioning with Ar
Nov 06 - commissioning of purifier and membranes
Dec 06 - closed-loop operation possible
April 07 - full commissioning with Xe (analysis,
recovery)

23
Recovery Plant / Monitoring

ALEPH recovery plant relocated, needs to be
re-commissioned
compressor unit for recovered gas still to be
designed and produced

drift velocity monitor under test
24
PASA Overview
H.-K. Soltveit, HD
PASA productionfinished125,000 chipstested
(almosttwice as many asneeded) yield 99
Microscope
Control area
Chuck, needle card, needle card adapter and wafer
Main PASA tester
25
TRAP Overview

wafers from 2 engineering runs with good yield
( 80)
first production run poor yield ( 30) and
difficult to bond
corner run proposed by foundry
received back in February ( 50)
have enough good chips for first super module
two further production slots reserved in 2006
(prices dropping significantly)

26
TRAP Tests (Wafer/MCM)
V. Angelov, F. Ferner, D. Gottschalk, HD

Power - reject chips with high currents
Digital part
Connectivity test using JTAG (MCM only)
Contact resistances of some signals (wafer only)
Internal tests using internal CPUs instruction
memories, data memory, configuration
registers, CPU registers, look up tables, digital
filters etc.
Test the readout-tree functionality

Analog part
internal pulser of PASA used to test ADCs (MCM
only)
Sine-wave test of 50 of ADCs on wafer (wafer
only)
Reliability test using different digital supply
voltages

MCM tester
needle card of wafer tester
27
TRAP Performance
M. Gutfleisch, HD

performs angle reconstruction
good agreement with offline tracking

28
MCM Production
Th. Blank, FZK

originally FZ Karlsruhe as sole producer
anticipated
encountered bonding problems (bonder reliability
issues, contacts)
found alternative producer - attractive pricing
(MSC) (ROB producer)
optimized bonding procedure and balling of MCMs
split contract between FZ Karlsruhe and MSC (50
TRD)
agreement to build 15000 modules at FZK
25000 modules at MSC (delivery schedule to be
settled end of March)
current production rate at FZK 800 MCM/wk (gt1
layer/wk) - yield 90
FZK will complete 25 by April
MCM production rate sufficient for ROB and SM
production

29
ROB Test Setup _at_ HD
J. Mercado. HD

ROB tests
power consumption
SCSN functionality
internal TRAP
tests
IMEM, DBANK, DMEM, DIV, CJP,
CST, PG, GIO, IRQ, LUT, EBF, Filters, . . .
network interface test (read-out tree) via SCSN

30
ROB Production/Test Status
I. Rusanov. HD Th. Blank, FZK
design finished - Nov 052 qualified offers - Dec
05delivery - Jan/Feb 06contract to be awarded
end of March
Origin Delivery ROB types Items Tested Good
FZK 12/2005 3A, 3B, 4A, 4B 19 all 18
FZK 19.01.2006 1B, 2B, 3A 18 all 16
Dommel 20.01.2006 2B 9 all 9
FZK 27.01.2006 1A 13 all 11
MSC 06.02.2006 1B 10 all 9
FZK 10.02.2006 all types 30 all 24
ROBs ready and tested as of Feb, 28 76 (2
layers) Yield 86
31
Electronics Integration
Chr. Lippmann, GSI K. Oyama, D. Emschermann. HD
L0C1 003

ROCs in various stages of completion
assembly procedure documented
knowledge base of errors (missing grounds, etc.)
workload 2 person days / chamber
one layer finished

in super module
32
Noise Performance
Chr. Lippmann, GSI K. Oyama, I. Rusanov, HD

Latest measurement ltRMSgt 1.17 LSB1230 e
stable over many days
with
Wiener P.S. for ROBs.
CERES P.S. for DCS.
Power bus bar (C.L. type).

33
High Voltage Master/Slave System
Athens University
Controls
6-ch. card / top viewauxiliary power supply box
34
HV System Status
First system test at HD (Feb 23 - 25)- anode
voltages (2000 V) - 6 channels successfully
tested- stability 50mV- full command access
through CAN (and serial interface)- first PVSS
FSM functions error handling available -
primary HV supplies available for 12 super
modules To do - negative voltages (-3000 V)-
software regulation w/ 16 bit ADC _at_10-15Hz ?
5mV Goal- full test of 1st SM equipment at
HD/KIP (end of May)
35
Detector Control System (DCS)
D. Gottschalk, K. Schweda, J. Mercado, HD M.
Stockmeier, R. Bramm, GSI
DCS Hardware Link http//www.kip.uni-heidelber
g.de/ti/DCS-Board/current/

Each DCS board controls eight readout boards
Monitoring functions
temperature of MCMs
currents of MCMs
Control functions
voltage regulator shutdown
MCM configuration
Clock and Trigger Distribution

Optical Clock Receiver (TTCrx)
Ethernet link
JTAG in and JTAG out
8 analog inputs 16 Bit / 10Sps
8 Pseudo LVDS Inputs
8 Pseudo LVDS Outputs
24 Switching Lines
two 8 Bit Ports (optionally)
I²C Bus
two-wire UART
autonomous power supply

DCS interface functionality
36
DCS Status
200 TPC DCS boards delivered by MSC 215 TRD DCS
boards expected end of March rest in April 120
TRD DCS boards programmed and successfully
tested PVSS control chain tested Database access
being worked on
37
Optical Sender Status
V. Angelov, HD

Test setup
Read-out board
? Optical Sender Board
? 60m long fiber
? dedicated test receiver board
? ACEX PCI card software
Latest test results
Bit error rates below 10-12 (upper limit)
Current stock
12 Optical Sender Boards built and tested
components radiation tested - 2 weeks ago

ORI on ROB 3A/B
Optical receiver on the ACEX board
38
TRD Trigger
J. DeCuveland, HD
Global Tracking Inside GTU (Global Tracking
Unit) Objective find high momentum
tracks Search for tracklets belonging
together Combine tracklets from all six
layers Reconstruct pt, compare to threshold and
generate trigger Constraintonly approx. 1.5
µs processing time
Charge Cluster to Tracklet Local tracking units
on detector perform linear fits and reject
uninteresting data
Tracklet(32-Bit word) y position
(origin) slope (deflection) z position
(pad-row number) charge

Trigger decision after 6 µs
Charge drift and data pre-processing uses most of
the time

39
TMU Board Prototype Status

basic PCB functionality successfully tested
all supply voltages, oscillators
configuration flash PROM, FPGA configuration via
JTAG
system monitoring and user I/O via I2C
SFP module controlling via I2C
multi-gigabit transceiver (MGT) operation shown
in principle
transmission between two GTU boards working (with
limitations)
known bug in Xilinx Virtex-4 FX60 engineering
sample-1 chips PLLs lose lock, need prototype
with ES4 chips
next to be tested
SRAM
CompactPCI interface
LVDS to backplane

40
TMU Design / Simulation
Reconstruction Precision
pt reconstruction precision 2.1
TMU Processing Time
Detection Efficiency
Simulation with Altera FPGA at 40 MHz Final
design using Xilinx Virtex-4 FX at gt 60 MHz
Simulations with AliRoot data, electrons with
pt gt 3 GeV/c
Results depend on multiplicity density dNch/d?
and number of tracklets delivered by detector
41
TRD Pre-Trigger System
K. Oyama, R. Schicker, HD

TRD pre-trigger wakeup signal sent to TRD
MCMs
generated by T0, V0 and TOF
T0 Timing detector and M.B. trigger
V0 Vertex detection and pp trigger
TOF cosmic trigger and low multiplicity
(ultra-peripheral)
timing crucial ? system placed inside L3 magnet
duplicated for fault tolerance
functionality of pre-trigger system
generates coincidence signal of T0, V0 and TOF
detectors
distribution of TTC signal from CTP and into
TRD TTC stream
provides TTC optical signals to 18 TRD
super-modules
generates control signals for FSM in MCMs

42
Pre-Trigger Schematics
K. Oyama, HD
43
Pre-Trigger Timing/Data Flow
44
T0/V0 Pre-Amplifier Module
K. Oyama, PI Electronics Shop, HD
x10 output
x1 feed-through output
final design 55mm x 55mm 3 SMA connectors P0.5
W/ch
power
differential output to TRD pre-trigger system
input from the PMT
30 ps resolution achieved in test beam
experiment high ground and power stability
required circuit contains inductance - still
operational at B0.5 T
45
Location of Pre-Trigger Components
inner bar (7m)
A
C
TRD
FEB
FEB
FEB
FEB
FEB
FEB
FEB
FEB
FEB
FEB
T0-C
T0-A
CB-C
CB-A
CB-TOF
TOF signals
46
Prototype Control Board
K. Oyama, PI Electronics Shop, HD
all components will be locatedinside L3 volume
(back frame,baby space frame)
DCS board
47
Detector Summary

construction of TRD moving steadily ahead
5 sites working on chamber production
excellent understanding of detector performance
from test beam data (6 NIM publications last
year)
rail system installed in space frame
final alignment and insertion test (March-May)
first assembly of super module structure
successful
integration ongoing
first super module ready for installation in July
looking forward to funding commitment for 100
inearly 2006

48
Electronics Summary