FAULTTOLERANT, REALTIME RECONFIGURABLE PREFIX ADDER

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FAULT-TOLERANT, REAL-TIME RECONFIGURABLE PREFIX
ADDER

• Marisabel Guevara and Chris Gregg
• ECE-632, Fall 2008

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ERRORS IN COMPUTATIONAL LOGIC

• Faster, Smaller, Better?

Technology Scaling
Greater Rate of Errors
Soft Errors
Hard Errors
Alpha Particles
Cosmic Rays
Variation
Material Defects
Physical Failure
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ERRORS IN COMPUTATIONAL LOGIC

• Solution? Catch the errors (and correct them,
  too)

Area
Triple Modular Redundancy
Standard Circuit (fault vulnerable)
Error Correcting Logic
Delay
Triple Modular Redundancy
Standard Circuit (fault vulnerable)
Error Correcting Logic
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ERROR DETECTING/TOLERATING

• Microprocessor Components
• Memory
• ALU
• Interconnect, Logic Blocks, etc.

• Errors can be detected using logic (e.g.,
  parity), but then need to be corrected
• However, adders suffer from fault aliasing
• Errors can be tolerated using Triple Modular
  Redundancy

Fault!
0 1 1 0
0 1 1 1
0111
0111
0011
0011
1001
1010
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PREFIX ADDER ERROR CORRECTION

• The Kogge-Stone Adder is fast, but its speed is
  attained by utilizing inherent redundancy.
• A Kogge-Stone Adder has enough redundancy that
  the addition of a single extra level of dot
  operators produces two Han-Carlson adders, each
  of which will produce independent carries along
  separate paths (i.e., if there is a single fault,
  the complete carry output can be recovered from
  either an odd or even Han-Carlson adder.

Ndai, P. Lu, S. Somesekhar, D. Roy, K.
Fine-Grained Redundancy in AddersQuality
Electronic Design, 2007. ISQED '07. 8th
International Symposium on, 2007, 317-321
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IN BRIEF KOGGE-STONE -VS- HAN-CARLSON ADDERS

• Kogge-Stone Adders have a delay proportional to
  log2N.
• Han-Carlson Adders have a delay proportional to
  log2N1

4-bit Kogge-Stone
4-bit Han-Carlson
Ndai, P. Lu, S. Somesekhar, D. Roy, K.
Fine-Grained Redundancy in AddersQuality
Electronic Design, 2007. ISQED '07. 8th
International Symposium on, 2007, 317-321
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PREFIX ADDER ERROR CORRECTION
Ndai, P. Lu, S. Somesekhar, D. Roy, K.
Fine-Grained Redundancy in AddersQuality
Electronic Design, 2007. ISQED '07. 8th
International Symposium on, 2007, 317-321
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PREFIX ADDER ERROR CORRECTION

• Error correction logic depends on parity checking
  of the Kogge-Stone and Han-Carlson Output

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PREFIX ADDER ERROR CORRECTION

• Error correction logic depends on parity checking
• We utilized a minimized priority encoder to
  choose the correct side (odd or even) in the
  event of a fault.

8-bit Minimized Priority Encoder
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FAULT-TOLERANT, REAL-TIME RECONFIGURABLE ADDER
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RESULTS

• Delay Overhead
• 4-bit ? 0.8 ns, 16-bit ? 0.7 ns
• Higher bit-count adders will incur smaller delay
  cost
• KSA ? O(log2N)
• Proposed KSA ? O(log2N 1)
• Priority encoder bound by O(log2N)
• Hardware Overhead

Kun, C. Quan, S. Mason, A. A power-optimized
64-bit priority encoder utilizing parallel
priority look-ahead. Circuits and Systems, 2004.
ISCAS '04. Proceedings of the 2004 International
Symposium on, 2004, 2, II-753-6 Vol.2
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SIMULATION RESULTS
Delay of 4-bit fault-tolerant KSA
Delay of 16-bit fault-tolerant KSA
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CONTRIBUTIONS AND FUTURE WORK

• Real-time reconfigurable prefix adder
• Guarantees detection and correction of a
  single-fault
• Correct up to 50 of bits in the event of
  multiple errors
• Could be extended to other PPAs
• Advances research in fault-tolerant logic blocks
• Provides high-reliability applications an
  alternative with different delay and area
  trade-offs
• Top 6 candidates for nanoscale electronics are
  all vulnerable to noise and errors

Rao, W. Orailoglu, A. Towards fault tolerant
parallel prefix adders in nanoelectronic systems.
Design, Automation and Test in Europe, 2008.
DATE '08, 2008, 360-365
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QUESTIONS?