Microprocessor System Design

1
Microprocessor System Design

• Omid Fatemi
• 8088 Microprocessor
• (omid_at_fatemi.net)

2
Outline

• Moores law
• 80x86 history
• Pin configuration
• Minimal / Maximal mode
• Address latch enable
• Bi-directional data bus

3
Computer modules
Keyboard Monitor Printer Mouse Microphone Disk
CPU
Memory (RAM, ROM)
Peripherals (IO)
4
Intels Microprocessors and Moores law
5
From Intel Site
http//www.intel.com/pressroom/archive/backgrnd/30
thann_funfacts.htm

• It all started 30 years ago, November 1971
• Intel began development of the first
  microprocessor in 1969 as part of a project to
  design a set of chips for a family of
  programmable calculators from Japanese calculator
  manufacturer Busicom.
• Originally, Busicom owned the rights to the
  microprocessor having paid Intel 60,000.
  Realizing the potential for the "brain" chip,
  Intel offered to return the 60,000 in exchange
  for the rights to the microprocessor design.
• Busicom agreed and Intel introduced the 4004 to
  the worldwide market on November 15, 1971. The
  4004 sold for 200 each. The key to the success
  of the microprocessor idea was to provide a
  software programmable device. Prior to the
  invention of the programmable microprocessor,
  chips were designed to perform specific "fixed"
  functions.
• Today's state-of-the-art Pentium 4 Processor
• The latest direct descendant of the 4004 is the
  Intel Pentium 4 processor for desktop personal
  computers.
• Today's cutting edge Pentium 4 microprocessor
  operates at 2 billion cycles per second.
• It took 28 years to go from a speed of 108,000
  cycles per second performance in the 4004 brain
  chip to1 billion cycles per second (1 gigahertz)
  with the Intel Pentium III processor - and only
  18 months to break the 2 gigahertz barrier with
  the August announcement of the latest Pentium 4
  microprocessor.
• Pentium 4 processor-based personal computers (at
  price points ranging from under 1,000 to 2,000)
  are fueling the latest trends in home computing -
  from digital music and home digital movie making
  to photo-realistic 3D images and visual
  environments delivered on and off the net in
  advanced games, education and shopping
  experiences.

6
The Microprocessor

• An integrated circuit with millions of
  transistors interconnected with very small
  aluminum wires.
• Controls and directs activities of the PC
• Execute stored programs

7
Von Neumann Architecture
Memory
Microprocessor
Address Lines
Actual Processor
Program
Data Lines
Data
Registers
Control Lines
8
The 8086 FamilyThe Late 1970s

• Could address up to 1 mb of memory at a time when
  other CPUs could only address 64 kb. The 16 bit
  external bus too powerful.
• The 8088 replaced the 8086 and had only an 8 bit
  external bus
• The 8088 CPU was the first chip used in IBMs
  microcomputers

9
The 80286 Family1983

• Wanted to make the 286 backward compatible with
  the 8088s.
• So had 2 modes
• Real mode-less powerful
• Protected mode-very powerful
• Could access up to 16 mb of memory
• Needed a special operating system
• But most users only had DOS

10
The 386 DX 1985

• First true 32 bit chip, all buses 32 bits wide
• Capable of running in real mode, 286 protected
  mode and its own 386 protected mode
• In 386 protected mode it had 2 new functions
• Virtual memory- could use hard drive to pretend
  that computer had up to 4 GB of data!
• Virtual 8086- 8086 bubbles created for DOS

11
The 386 SX1988

• How different from the 386DX?
• External data bus reduced to 16 bits
• Address bus reduced to 24 bits, which limited
  memory use to 16 mb
• First popular lap tops were based on the 386SX
  but was called the 386 SL and ran on 3.3 volts

12
The 486DX1989

• How different from the 386 family?
• A built in math coprocessor
• Performs high math functions
• A built in 8K cache on same chip
• This was an SRAM cache that stores code read in
  the past. When the CPU asks for the code again,
  it doesnt have to go to DRAM to get it.

13
486SX1991

• Same as 486 DX except the math co-processor is
  disabled.

14
The Pentiums1993

• Had 64 bit external data bus that split
  internally as 2 dual pipelined 32 bit buses
• Supported an 8K write through cache for programs
• Most early pentiums ran at 3.3 volts. This
  conserved heat. Voltage regulators on the
  motherboard can decrease voltage

15
Pentiums continued

• Includes clock doubling through the setting of
  jumpers
• Most later Pentuims use SPGA, Standard Pin Grid
  Array. This allows staggers the pens and allows
  for higher pen density

16
Pentium Pro(P6)1995

• Quad pipelining
• Dynamic processing
• On chip L2 cache
• Uses Socket 8

17
Recent PentiumsAfter 1996

• MMX- helps with multimedia products
• Increased multipliers/clocks- 45 multipliers
• Improved processing- better cache branch
  predicting
• Improved superscalar architecture
• SSE/SSE2 instructions

18
8088 Microprocessor

• Minimum Mode

19
Pin Configuration
20
Power and Ground Pins

• Vcc pin 40
• Gnd pin 1 and 20

21
Address Pins

• AD0..AD7
• A8..A15
• A19/S6, A18/S5, A17/S4, A16/S3

22
Data Pins

• AD0..AD7

23
Control Pins

• MN/MX (input)
• Indicates what mode the processor is to operate
  in
• READY (input)
• When given an input LOW, it will go into a wait
  state
• CLK (input)
• Provides basic timing for the processor
• RESET (input)
• Causes the processor to immediately terminate its
  present activity
• To reset the microprocessor, this must be HIGH
  for at least 4 clock cycles

24
Control Pins

• TEST (input)
• Connect this to HIGH
• HOLD (input)
• Connect this to LOW
• HLDA (output)

25
Control Pins

• INTR (input)
• Interrupt request
• INTA (output)
• Interrupt Acknowledge
• NMI (input)
• Non-maskable interrupt

26
Control Pins

• DEN (output)
• Data Enable
• It is LOW when processor wants to receive data or
  processor is giving out data
• DT/R (output)
• Data Transmit/Receive
• When HIGH, direction of data lines is from
  microprocessor to memory/devices
• When LOW, direction of data lines is from
  memory/devices to microprocessor
• IO/M (output)
• Device/Memory
• When HIGH, microprocessor wants to access I/O
  Device
• When LOW, microprocessor wants to access memory

27
Control Pins

• RD (output)
• When LOW, it indicates that the microprocessor is
  performing a read access
• WR (output)
• When LOW, it indicates that the microprocessor is
  performing a write access
• ALE (output)
• Address Latch Enable
• Provided by the microprocessor to latch address
• When this is HIGH, microprocessor is using
  AD0..AD7, A19/S6, A18/S5, A17/S4, A16/S3 as
  address lines

28
Clock Signal

• needed by the microprocessor to synchronize
  signals
• ideally a square wave having a constant frequency

29
8086 Signals
30
Providing Clock, Reset, and Ready Signal
31
Minimum Mode
32
Minimum Mode
33
Minimum Mode
34
Minimum Mode
D7 - D0
DEN
DT / R
A7 - A0
AD7 - AD0
A15 - A8
A19 - A16
A15 - A8
MEMORY
8088
A19/S6 - A16/S3
ALE
RD
RD
IO / M
WR
WR
35
Processor Timing Diagram of 8088 (Minimum
Mode)for Memory or I/O Read
T1
T2
T3
T4
CLOCK
__
DT/R
ALE
AD7 - AD0
A7 - A0
D7 - D0 (from memory)
A15 - A8
A15 - A8
A19/S6 - A16/S3
A19 - A16
S6 - S3
__
IO/M
if I/O ACCESS this is HIGH, if MEMORY ACCESS this
is LOW
____
RD
______
DEN
36
Will the circuit be able to perform memory read?

• assume that initially the values
• of the registers are
• BX 1234, DS 9000
• MOV AL, BX

37
Processor Timing Diagram of 8088 (Minimum
Mode)for Memory or I/O Read
T1
T2
T3
T4
CLOCK
__
DT/R
ALE
AD7 - AD0
A7 - A0
D7 - D0 (from memory)
A15 - A8
A15 - A8
A19/S6 - A16/S3
A19 - A16
S6 - S3
__
IO/M
if I/O ACCESS this is HIGH, if MEMORY ACCESS this
is LOW
____
RD
______
DEN
38
Minimum Mode
D7 - D0
DEN
DT / R
A7 - A0
AD7 - AD0
A15 - A8
A19 - A16
A15 - A8
MEMORY
8088
A19/S6 - A16/S3
ALE
RD
RD
IO / M
WR
WR
39
Minimum Mode
D7 - D0
DEN
DT / R
A7 - A0
AD7 - AD0
A15 - A8
A19 - A16
A15 - A8
MEMORY
8088
A19/S6 - A16/S3
ALE
RD
RD
IO / M
WR
WR
40
Octal Transparent Latch with 3-State Output
41
Processor Timing Diagram of 8088 (Minimum
Mode)for Memory or I/O Read
T1
T2
T3
T4
CLOCK
__
DT/R
ALE
AD7 - AD0
A7 - A0
D7 - D0 (from memory)
A15 - A8
A15 - A8
A19/S6 - A16/S3
S6 - S3
A19 - A16
A19 - A0
A19 - A0 from 74LS373
from 74LS373 to memory
__
IO/M
if I/O ACCESS this is HIGH, if MEMORY ACCESS this
is LOW
____
RD
______
DEN
42
Will the circuit be able to perform memory read?

• assume that initially the values
• of the registers are
• BX 1234, DS 9000
• MOV AL, BX

43
Processor Timing Diagram of 8088 (Minimum
Mode)for Memory or I/O Read (with 74373)
44
Minimum Mode
What about Data read and write
45
Minimum Mode
D7 - D0
DEN
DT / R
D7 - D0
Q7 - Q0
AD7 - AD0
A7 - A0
A15 - A8
OE
GND
A19 - A16
74LS373
LE
D7 - D0
Q7 - Q0
A15 - A8
MEMORY
OE
GND
74LS373
8088
LE
A19/S6 - A16/
D7 - D4
Q7 - Q4
S3
D3 - D0
Q3 - Q0
OE
GND
74LS373
ALE
LE
RD
RD
IO / M
WR
WR
46
Processor Timing Diagram of 8088 (Minimum
Mode)for Memory or I/O Read (with 74245)
47
Minimum Mode
48
Minimum Mode
49
Minimum Mode
50
Minimum Mode