IC??

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IC??

• ???
• ???? ??
• ???? ??
• ylin_at_cs.nthu.edu.tw

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Circuits

• Interconnected Network of Devices
• Resistors
• Capacitors
• Inductors
• Diodes
• Transistors
• AC/DC Current/Voltage Sources

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Transistors

• BJT (Bipolar Junction Transistor)
• FET (Field-Effect Transistor)
• Junction FET
• MOSFET (Metal-Oxide Semiconductor)
• PMOS
• NMOS
• CMOS (Complementary)

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Transistor Usage

• Signal Amplifier
• Voltage-Controlled Switch

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Hierarchy

• Switches form gate (AND, OR, NOT)
• Gates form module (Adder, Register)
• Modules form subsystem (Processor, I/O)
• Subsystems form system

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IC (Integrated Circuits)

• Discrete
• SSI (Small Scale Integration)
• MSI (Medium)
• LSI (Large)
• VLSI (Very Large)
• ULSI (Ultra Large)

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It all started with Moores Law

• Number of transistors on a chip doubles every 18
  months
• CPU performance doubles every 18 months
• Memory density quadruples every 3 years
• Fab cost doubles every generation
• Wealth doubles every ???

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Intel Processors FollowMoores Law
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K, M, G, and T

• 1970
• K-bit RAM, KIPS processor, K-bps link
• 1985
• M-bit RAM, MIPS processor, M-bps link
• 2000
• G-bit RAM, GIPS processor, G-bps link
• 2015?
• Tera-bit RAM, TIPS processor, T-bps link

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Pentium II
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Relative Processor Size
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A Blowfish Cipher
The Outstanding Design Award, ASP-DAC-2000
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IC Conductors
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IC Applications

• Computing
• PC, Servers, Peripherals
• Communication
• Telecom, Mobile Phone, Networking
• Consumer
• Auto, Game Console, DSC, CD/VCD/DVD, STB, HDTV,
  Home Networking, Toys
• 3C Convergence
• PDA, GPS, Information Appliance

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IC Everywhere

• Car ECU, ABS, GPS, AV, Toll Collection
• Home Entertainment, Security, Education
• Body Hearing Aid, HB Regulator, Monitor
• RF ID, Pico Radio (Last meter)
• IC will Smarten Everything
• Taiwan Imports more IC than Petroleum

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Convergence
Watch
Mobile Phone Set
Phone
Wrist Watch
Game
PalmPilot
Pet
???
Video Conf.
Tamagotchi
???
Clothes
???
TV
SmartPen
Radio
WalkMan
PDA
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IC and Applications
Make Possible More
IC Capability
Applications
Demand More
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IC Economics

• ?????
• Unit cost NRE/Volume Unit Manu Cost
• Typical NRE a few M USD
• One 8 wafer ( 300,000mm2) contains 3,000
  100mm2 dies
• Each wafer costs 2,000 to make
• Chip price ranges from 3 to 300
• Design is the difference

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IC Categories

• Memory
• SRAM, DRAM, ROM, FLASH
• Processors
• MPU, DSP, uC
• Logic
• Chip-set, Graphics
• Analog
• RF, IF, A/D, D/A
• System-on-a-Chip (SOC)

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System-on-a-Chip (SOC)
RISC
DSP
RAM
ROM
Logic
MPEG
I/O
MEMS
RF
Analog
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Top 10 Chip Companies in 1999

• Intel 25.81B
• NEC 9.216B
• Toshiba 7.594B
• Samsung 7.095B
• TI 7.095B

• Motorola 6.425B
• Hitachi 5.521B
• STMicro 5.080B
• Philips 5.065B
• Infineon 5.010B

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IC Industry Segments
IC Design Houses
Manufacturing, Packaging, Testing Foundry
IC Users
Library/IP Vendor
EDA Vendor
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Terminology

• Wafer
• 6, 8, 12
• Die
• Manufactured, Sawed wafer
• Chip
• Packaged die
• Minimum Feature Size
• 0.5um, 0.35um, 0.25um, 0.18um, 0.15um, 0.13um

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Taiwan IDM

• Winbond
• Macronix (MXIC)
• Holtek (Gone)
• SiS (Coming)
• HuaLon (?)

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Taiwan Fabless IC Houses

• PC Chip-set
• SiS, VIA, Ali
• Memory
• ETRON, UTRON
• Consumer
• Sun-Plus, Myson, MediaTek
• Network
• Realtek, TOPIC

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EDA Vendors

• Cadence
• Synopsys
• Avant!
• Mentor Graphics
• SpringSoft

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IC Design Process

• Specification Definition
• Front-end Design
• Prototyping
• Back-end Design
• Verification
• Test Generation
• Characterization QA

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IC Design Objectives

• Functionality
• Area Efficiency
• Performance (Speed)
• Power Consumption
• Testability
• Manufacturability (Yield Enhancement)
• Time-to-Market, -Volume, -Profit

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Design Entry

• Schematic Drawing
• HDL Coding
• Productivity Tool (e.g., DeBusy from SpringSoft)
• Domain Specific (e.g., SPW)
• MATLAB, FSM
• Hardware/Software Codesign

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Synthesis

• Synthesis for Area, Speed, and Power, and
  Tradeoff
• Design for Testability by Scan Insertion
• Automatic Test Pattern Generation

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Layout

• Floorplanning
• Placement
• Routing
• In-Place Optimization ECO
• Clock Tree Synthesis
• Power Rail Synthesis
• Compaction Layout Migration

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Simulation

• Functional(RTL) Simulation
• Logic (Gate-Level) Simulation
• Pre-Layout Simulation
• Post-Layout Simulation
• Circuit Simulation
• Power Simulation
• Fault Simulation

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Verification

• Formal, Semi-Formal Verification of Functionality
  and ECO Change
• Timing Verification True Critical Path
  Identification (Static Timing Analysis)
• Crosstalk Noise Verification
• Layout Verification

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Layout Verification

• Design Rule Checking(DRC)
• Electrical Rule Checking(ERC)
• Layout vs Schematic (LVS)
• Antenna Rule Checking
• Electrical Migration Checking
• Metal Density Checking

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Layout Extraction

• Parasitic R, C, L
• 2D, Quasi 2D, 3D Extraction
• Extracted Parasitic Reduction
• Delay Calculation Noise Analysis
• Back Annotation

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VLSI Design Challenges

• Complexity
• Multi-Million Xtors (16M in P/S2 EE)
• Mixed Digital/Analog/RF
• Mixed Logic/Memory
• Hardware/Software Co-design
• Very Deep-Submicron Effect
• Wire Delay Dominant, but unknown during front-end
  design stage

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Facing the Challenges

• New Design Methodology
• Platform-Based
• Reuse Silicon Intellectual Properties(IP)
• Internet

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Platform-Based Design
IP
IP
IP
IP
Communication Backplane
IP
IP
IP
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IC Industry Segments
IC House
Manufacturing Foundry
IC User
Library Vendor
IP Vendor
IP Vendor
IP Vendor
Design Foundry IP Outlet
EDA Vendor
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Notable IP Vendors

• ARM, MIPS, DSP-Group, LSI Logic, IBM
• Phoenix, Zoran, Virtual IP, Artisan
• Tensilica, ARC Cores
• UniChip, Faraday, SOTA

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ARM (Advanced RISC Machine)

• Chipless Chip Company
• License CPU technology to semiconductor houses
• 8M per core or 0.5M per design 0.5 per chip
  royalty
• Very popular in portable applications
• Market cap gt 20B

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RAMBUS

• High-Speed Protocol Between DRAM and Processor
• Burns 100M over 7 years
• Chipless, 3 royalty of all DRAM sale

CPU
DRAM
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Global Unichip

• Design Foundry with IP Offering
• Top Design Talent
• IP
• JPEG Encoder, CODEC for DSC, Scanner, PC Cam
• DSP
• USB
• Embedded Memory

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IP Requirement

• Competitive in functionality, size, power, or
  performance
• Well Characterized (Silicon verified)
• Integratable (Documents, executable models,
  confirmed to standards)
• Test Strategy implementable by the SOC
• Unambiguous boundary of responsibility

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IP Enabler

• Channels for small IP creators
• One-stop shopping window for IC creators
• Combining design service and IP vending

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Star IP

• Extremely low-power DSP, uP, uC
• Media-processing cores (A/V, JPEG, MPEG)
• Up-and-coming mainstream interface cores (USB2.0,
  1394, Networking)
• Very high density memory macros

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Internet and IC Design

• Distributed Collaboration
• Distributed IP Library
• Distributed EDA Resource

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Today's Design Environment
Design Data
Tools
IP
Consulting Info. Service Industry News Company
Expertise PC Networks Office Automation
Library
Outside Resources
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Today's Users

• Buy Computers
• Buy Software (Or Develop In-House)
• Hire Supporting Staffs
• Pay for Operation and Maintenance
• Inflexible
• Under Utilized or Overloaded

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User's Concerns

• Availability
• Throughput, Turn-Around Time
• Security
• Cost

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Future Internet-Centric Design Environment
Industry News
Libraries
Tools
On-Line Experts
Design Data
Information Service
Company Knowledge Base
Intellectual Properties
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Elements of Computing

• Computers
• (Hardware System Software)
• Software
• (Tools, Application Programs)
• Data

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Taxonomy
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Pay-per-Use in the Old Days
Client Site
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Broker-Centric Environment
Clients
Vendors
Hardware
Software
InterNet
Reusable Design
Broker
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Pay-per-Use

• Buy Service, Instead of Properties
• No Ownership Cost
• Use Anything as Much as You Need to
• Pay only after You Use
• Immediate Access to Latest and Best HW/SW
  Technologies

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WWW over Internet

• Universal availability
• Enable seamless access, via hyperlinks, to data
  and software on file systems throughout the world
• A new interface between producers and consumers
  of goods and service
• Numerous emerging applications commerce,
  education, entertainment, ...

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Multi-Tiered Client Server
Tier 2 Application Server
Application Server
Web Server
Internet Browser
Tier 3 User Interface Client
Database
Tier 1 Database Server
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Web-Based CAD Activities

• PPP -- Stanford
• Synthesis, Simulation, Optimization
• PowerPlay -- Berkeley
• Low Power Architectural Design
• WELD -- Berkeley
• FSM Synthesizer in JAVA
• WADE -- Northwestern
• Parallel Placement
• ComBro -- Tsing Hua University
• Brokerage

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The THEDA Computing Brokerage Project

• Tsing Hua Electronic Design Automation (THEDA)
  Group
• WWW-Based
• 20 Sun SparcStations
• Verilog-XL, HSPICE, SIS ...
• http//theda.cs.nthu.edu.tw

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Resources Managed by the Broker

• Computing Time
• Software Usage
• Library
• Design Knowledge
• Storage Facility

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Broker

• One-Stop Service
• Leverage over Utilization and Availability
• Confidential Issues (Trade Secrete)
• Scheduling Policy
• Pricing Strategy
• Accounting and Billing

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Vendors

• Less Marketing Effort, No Shipping, No Field
  Service
• Niche for the Best, the Least Expensive, and
  anything in between
• Good Chance for Newcomers

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User Request

• Tool Name, Input Data Files, Output Data Files
• Optional Computer Type, Configuration, OS Version
  etc..
• Class of Service
• Get Quotation
• Advanced Reservation

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40 forces that will shape the industry (IC_at_40,EE
Times)
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Summary

• IC Everywhere
• IC Value Comes from Design
• IC Design Will be the Next Wave of Taiwan
  Semiconductor Industry
• Design is Getting Difficult
• IP and Design Foundry Will Play an Important Role