CMOS VLSI Design

1
CMOS VLSI Design

• Digital Design

2
Overview

• Physical principles
• Combinational logic
• Sequential logic
• Datapath
• Memories
• Trends

3
Dopants

• Silicon is a semiconductor
• Pure silicon has no free carriers and conducts
  poorly
• Adding dopants increases the conductivity
• Group V extra electron (n-type)
• Group III missing electron, called hole (p-type)

4
nMOS Operation

• Body is commonly tied to ground (0 V)
• When the gate is at a low voltage
• P-type body is at low voltage
• Source-body and drain-body diodes are OFF
• No current flows, transistor is OFF

5
Transistors as Switches

• We can view MOS transistors as electrically
  controlled switches
• Voltage at gate controls path from source to drain

6
CMOS Inverter
A Y
0
1
7
Inverter Cross-section

• Typically use p-type substrate for nMOS
  transistors
• Requires n-well for body of pMOS transistors

8
Inverter Mask Set

• Transistors and wires are defined by masks
• Cross-section taken along dashed line

9
Fabrication Steps

• Start with blank wafer
• Build inverter from the bottom up
• First step will be to form the n-well
• Cover wafer with protective layer of SiO2 (oxide)
• Remove layer where n-well should be built
• Implant or diffuse n dopants into exposed wafer
• Strip off SiO2

10
Oxidation

• Grow SiO2 on top of Si wafer
• 900 1200 C with H2O or O2 in oxidation furnace

11
Photoresist

• Spin on photoresist
• Photoresist is a light-sensitive organic polymer
• Softens where exposed to light

12
Lithography

• Expose photoresist through n-well mask
• Strip off exposed photoresist

13
Etch

• Etch oxide with hydrofluoric acid (HF)
• Seeps through skin and eats bone nasty stuff!!!
• Only attacks oxide where resist has been exposed

14
Strip Photoresist

• Strip off remaining photoresist
• Use mixture of acids called piranah etch
• Necessary so resist doesnt melt in next step

15
n-well

• n-well is formed with diffusion or ion
  implantation
• Diffusion
• Place wafer in furnace with arsenic gas
• Heat until As atoms diffuse into exposed Si
• Ion Implanatation
• Blast wafer with beam of As ions
• Ions blocked by SiO2, only enter exposed Si

16
Simplified Design Rules

• Conservative rules to get you started

17
Complementary CMOS

• Complementary CMOS logic gates
• nMOS pull-down network
• pMOS pull-up network
• a.k.a. static CMOS

Pull-up OFF Pull-up ON
Pull-down OFF Z (float) 1
Pull-down ON 0 X (crowbar)
18
Example NAND3

• Horizontal N-diffusion and p-diffusion strips
• Vertical polysilicon gates
• Metal1 VDD rail at top
• Metal1 GND rail at bottom
• 32 l by 40 l

19
I-V Characteristics

• In Linear region, Ids depends on
• How much charge is in the channel?
• How fast is the charge moving?

20
Channel Charge

• MOS structure looks like parallel plate capacitor
  while operating in inversion
• Gate oxide channel
• Qchannel CV
• C Cg eoxWL/tox CoxWL
• V Vgc Vt (Vgs Vds/2) Vt

Cox eox / tox
21
Carrier velocity

• Charge is carried by e-
• Carrier velocity v proportional to lateral
  E-field between source and drain
• v mE m called mobility
• E Vds/L
• Time for carrier to cross channel
• t L / v

22
nMOS Linear I-V

• Now we know
• How much charge Qchannel is in the channel
• How much time t each carrier takes to cross

23
Example

• Example a 0.6 mm process from AMI semiconductor
• tox 100 Å
• m 350 cm2/Vs
• Vt 0.7 V
• Plot Ids vs. Vds
• Vgs 0, 1, 2, 3, 4, 5
• Use W/L 4/2 l

24
Capacitance

• Any two conductors separated by an insulator have
  capacitance
• Gate to channel capacitor is very important
• Creates channel charge necessary for operation
• Source and drain have capacitance to body
• Across reverse-biased diodes
• Called diffusion capacitance because it is
  associated with source/drain diffusion

25
Gate Capacitance

• Approximate channel as connected to source
• Cgs eoxWL/tox CoxWL CpermicronW
• Cpermicron is typically about 2 fF/mm

26
Diffusion Capacitance

• Csb, Cdb
• Undesirable, called parasitic capacitance
• Capacitance depends on area and perimeter
• Use small diffusion nodes
• Comparable to Cg
• for contacted diff
• ½ Cg for uncontacted
• Varies with process

27
RC Delay Model

• Use equivalent circuits for MOS transistors
• Ideal switch capacitance and ON resistance
• Unit nMOS has resistance R, capacitance C
• Unit pMOS has resistance 2R, capacitance C
• Capacitance proportional to width
• Resistance inversely proportional to width

28
Introduction

• Chips are mostly made of wires called
  interconnect
• In stick diagram, wires set size
• Transistors are little things under the wires
• Many layers of wires
• Wires are as important as transistors
• Speed
• Power
• Noise
• Alternating layers run orthogonally

29
Wire Capacitance

• Wire has capacitance per unit length
• To neighbors
• To layers above and below
• Ctotal Ctop Cbot 2Cadj

30
Lumped Element Models

• Wires are a distributed system
• Approximate with lumped element models
• 3-segment p-model is accurate to 3 in simulation
• L-model needs 100 segments for same accuracy!
• Use single segment p-model for Elmore delay

31
Crosstalk

• A capacitor does not like to change its voltage
  instantaneously.
• A wire has high capacitance to its neighbor.
• When the neighbor switches from 1-gt 0 or 0-gt1,
  the wire tends to switch too.
• Called capacitive coupling or crosstalk.
• Crosstalk effects
• Noise on nonswitching wires
• Increased delay on switching wires

32
Coupling Waveforms

• Simulated coupling for Cadj Cvictim

33
Introduction

• What makes a circuit fast?
• I C dV/dt -gt tpd ? (C/I) DV
• low capacitance
• high current
• small swing
• Logical effort is proportional to C/I
• pMOS are the enemy!
• High capacitance for a given current
• Can we take the pMOS capacitance off the input?
• Various circuit families try to do this

34
Pseudo-nMOS

• In the old days, nMOS processes had no pMOS
• Instead, use pull-up transistor that is always ON
• In CMOS, use a pMOS that is always ON
• Ratio issue
• Make pMOS about ¼ effective strength of pulldown
  network

35
Dynamic Logic

• Dynamic gates uses a clocked pMOS pullup
• Two modes precharge and evaluate

36
Pass Transistor Circuits

• Use pass transistors like switches to do logic
• Inputs drive diffusion terminals as well as gates
• CMOS Transmission Gates
• 2-input multiplexer
• Gates should be restoring

37
Sequencing

• Combinational logic
• output depends on current inputs
• Sequential logic
• output depends on current and previous inputs
• Requires separating previous, current, future
• Called state or tokens
• Ex FSM, pipeline

38
Sequencing Overhead

• Use flip-flops to delay fast tokens so they move
  through exactly one stage each cycle.
• Inevitably adds some delay to the slow tokens
• Makes circuit slower than just the logic delay
• Called sequencing overhead
• Some people call this clocking overhead
• But it applies to asynchronous circuits too
• Inevitable side effect of maintaining sequence

39
Sequencing Elements

• Latch Level sensitive
• a.k.a. transparent latch, D latch
• Flip-flop edge triggered
• A.k.a. master-slave flip-flop, D flip-flop, D
  register
• Timing Diagrams
• Transparent
• Opaque
• Edge-trigger

40
Latch Design

• Buffered output
• No backdriving
• Widely used in standard cells
• Very robust (most important)
• Rather large
• Rather slow (1.5 2 FO4 delays)
• High clock loading

41
Sequencing Methods

• Flip-flops
• 2-Phase Latches
• Pulsed Latches

42
Summary

• Flip-Flops
• Very easy to use, supported by all tools
• 2-Phase Transparent Latches
• Lots of skew tolerance and time borrowing
• Pulsed Latches
• Fast, some skew tol borrow, hold time risk

43
Full Adder Design I

• Brute force implementation from eqns

44
Carry-Skip Adder

• Carry-ripple is slow through all N stages
• Carry-skip allows carry to skip over groups of n
  bits
• Decision based on n-bit propagate signal

45
Tree Adder

• If lookahead is good, lookahead across lookahead!
• Recursive lookahead gives O(log N) delay
• Many variations on tree adders

46
Memory Arrays
47
Array Architecture

• 2n words of 2m bits each
• If n gtgt m, fold by 2k into fewer rows of more
  columns
• Good regularity easy to design
• Very high density if good cells are used

48
6T SRAM Cell

• Cell size accounts for most of array size
• Reduce cell size at expense of complexity
• 6T SRAM Cell
• Used in most commercial chips
• Data stored in cross-coupled inverters
• Read
• Precharge bit, bit_b
• Raise wordline
• Write
• Drive data onto bit, bit_b
• Raise wordline

49
SRAM Sizing

• High bitlines must not overpower inverters during
  reads
• But low bitlines must write new value into cell

50
Decoders

• n2n decoder consists of 2n n-input AND gates
• One needed for each row of memory
• Build AND from NAND or NOR gates
• Static CMOS Pseudo-nMOS

51
Decoder Layout

• Decoders must be pitch-matched to SRAM cell
• Requires very skinny gates

52
Sense Amplifiers

• Bitlines have many cells attached
• Ex 32-kbit SRAM has 256 rows x 128 cols
• 128 cells on each bitline
• tpd ? (C/I) DV
• Even with shared diffusion contacts, 64C of
  diffusion capacitance (big C)
• Discharged slowly through small transistors
  (small I)
• Sense amplifiers are triggered on small voltage
  swing (reduce DV)

53
Queues

• Queues allow data to be read and written at
  different rates.
• Read and write each use their own clock, data
• Queue indicates whether it is full or empty
• Build with SRAM and read/write counters
  (pointers)

54
CAMs

• Extension of ordinary memory (e.g. SRAM)
• Read and write memory as usual
• Also match to see which words contain a key

55
10T CAM Cell

• Add four match transistors to 6T SRAM
• 56 x 43 l unit cell

56
CAM Cell Operation

• Read and write like ordinary SRAM
• For matching
• Leave wordline low
• Precharge matchlines
• Place key on bitlines
• Matchlines evaluate
• Miss line
• Pseudo-nMOS NOR of match lines
• Goes high if no words match

57
ROM Example

• 4-word x 6-bit ROM
• Represented with dot diagram
• Dots indicate 1s in ROM

Word 0 010101 Word 1 011001 Word 2 100101 Word
3 101010
Looks like 6 4-input pseudo-nMOS NORs
58
PLAs

• A Programmable Logic Array performs any function
  in sum-of-products form.
• Literals inputs complements
• Products / Minterms AND of literals
• Outputs OR of Minterms
• Example Full Adder

59
PLA Schematic Layout
60
Ideal nMOS I-V Plot

• 180 nm TSMC process
• Ideal Models
• b 155(W/L) mA/V2
• Vt 0.4 V
• VDD 1.8 V

61
Simulated nMOS I-V Plot

• 180 nm TSMC process
• BSIM 3v3 SPICE models
• What differs?
• Less ON current
• No square law
• Current increases
• in saturation

62
Velocity Saturation

• We assumed carrier velocity is proportional to
  E-field
• v mElat mVds/L
• At high fields, this ceases to be true
• Carriers scatter off atoms
• Velocity reaches vsat
• Electrons 6-10 x 106 cm/s
• Holes 4-8 x 106 cm/s
• Better model

63
Channel Length Modulation

• Reverse-biased p-n junctions form a depletion
  region
• Region between n and p with no carriers
• Width of depletion Ld region grows with reverse
  bias
• Leff L Ld
• Shorter Leff gives more current
• Ids increases with Vds
• Even in saturation

64
Body Effect

• Vt gate voltage necessary to invert channel
• Increases if source voltage increases because
  source is connected to the channel
• Increase in Vt with Vs is called the body effect

65
OFF Transistor Behavior

• What about current in cutoff?
• Simulated results
• What differs?
• Current doesnt go
• to 0 in cutoff

66
Leakage Sources

• Subthreshold conduction
• Transistors cant abruptly turn ON or OFF
• Junction leakage
• Reverse-biased PN junction diode current
• Gate leakage
• Tunneling through ultrathin gate dielectric
• Subthreshold leakage is the biggest source in
  modern transistors

67
Low Power Design

• Reduce dynamic power
• a clock gating, sleep mode
• C small transistors (esp. on clock), short wires
  
• VDD lowest suitable voltage
• f lowest suitable frequency
• Reduce static power
• Selectively use ratioed circuits
• Selectively use low Vt devices
• Leakage reduction
• stacked devices, body bias, low temperature

68
Chip-to-Package Bonding

• Traditionally, chip is surrounded by pad frame
• Metal pads on 100 200 mm pitch
• Gold bond wires attach pads to package
• Lead frame distributes signals in package
• Metal heat spreader helps with cooling

69
Bidirectional Pads

• Combine input and output pad
• Need tristate driver on output
• Use enable signal to set direction
• Optimized tristate avoids huge series transistors

70
Device Scaling
71
Interconnect Delay