An Automated Design Flow for LowPower, HighThroughput Dedicated Signal Processing Systems

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An Automated Design Flow for Low-Power,
High-ThroughputDedicated Signal Processing
Systems
W. Rhett Davis, Ning Zhang, Kevin Camera, Dejan
Markovic, Tina Smilkstein, Nathan Chan, M. Josie
Ammer, Engling Yeo, Borivoje Nikolic, Robert W.
Brodersen

• http//bwrc.eecs.berkeley.edu

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Energy-Efficiency of Architectures
1000
Dedicated HW
Direct mapped 100-1000 MOPS/mW
100
ReconfigurableProcessor/Logic
Reconfiguration (???) Potential of 10-100 MOPS/mW
Energy Efficiency MOPS/mW (or MIPS/mW)
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1
Embedded mProcessors
Microprocessor .1-1 MIPS/mW
0.1
Flexibility (Coverage)
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Results in fully parallel solutions
Reducing supply voltage saves energy E CV2
(numbers taken from vendor-published
benchmarks) Orders of magnitude lower efficiency
even for an optimized processor architecture
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Standard DSP-ASIC Design Flow
Problems

• Three translations of design data
• Requirements for re-verification at each stage
• Uncontrolled looping when pipeline stalls

Prohibitively Long Design Time for Direct Mapped
Architectures
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Direct Mapping Design Flow
Algorithm/System
Simulation
Back-End
Front-End
Floorplan
RTL Libraries
Automated Flow
Mask Layout
Performance Estimates

• Encourages iterations of layout
• Controls looping
• Reduces the flow to a single phase
• Depends on fast automation

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Outline

• Chip-in-a-Day Flow
• User Perspective
• Design Decisions
• Estimation
• Automation
• Design Example
• Baseband Receiver
• Design Effort
• Problems

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Capturing Design Decisions

• Categories
• Function - basic input-output behavior
• Signal - physical signals and types
• Circuit - transistors
• Floorplan - physical positions

Layout and performance estimates in a day
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Performance Estimates

• Estimates vary in accuracy and execution time
• Different estimates should be available depending
  on how many decisions have been made

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Push-Button Automation

• Automation similar to MAKE
• No decisions made after button is pressed
• No translation of design data
• No decisions expressed more than once

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Example Multiple Graphs

• Early versions inferred pads from ports
• Another copy of design was maintained to examine
  internal signals (decisions expressed twice)
• Todays version allows SimOnly ports

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Choice of Computation Model

• Balance between conflicting needs
• Abstraction of Hardware (simulation speed)
• Clear Verification Strategy (detailed hardware)

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Example Dataflow Graph

• Discrete-Time(cycle accurate)
• Fixed-Point Types(bit true)
• No need for RTL simulation
• Embed macro choices
• Used SimulinkTM

Multiply / Accumulate
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Hierarchical Dataflow Graphs

• Want the hardware hierarchy to match dataflow
  graph hierarchy
• Grouping needed to hide complexity
• Referencing needed to save design effort

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Modeling Control Logic

• Extended finite state-machine editor
• Co-simulation with dataflow graph
• New SoftwareStateflow-VHDL translator
• No need for RTL

Address Generator / MAC Reset
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Floorplan Merged on Each Iteration
(Function, Signal, Circuit decisions)
(Floorplan decisions)
save the state
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Outline

• Chip-in-a-Day Flow
• User Perspective
• Design Decisions
• Estimation
• Automation
• Design Example
• Baseband Receiver
• Design Effort
• Problems

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TDMA Baseband Receiver

• DSSS TDMA w/ length 31 spreading code 25 MHz
  chip rate
• 806 kHz symbol rate, w/ QPSK gives 1.6 Mb/s data
  rate
• 7 bit I Q streams at 200 MHz, 8 parallel
  streams at 25 MHz

Q
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Design Effort

• Spec. Changes required no modification of
  datapath macros
• Routing began after 2 months
• No modification to dataflow graph from
  switch-level sims.
• Flow under development
• Reuse is crucial

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Automation Statistics

• Assuming automated flow and libraries are
  debugged, design time is little more than a day

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Chip Layout Plot

• 600k transistors
• 0.18 mm
• 1.0 V
• 25 MHz
• 3.7 mm x 3.7 mm(w/ pads)
• 1.8 mm x 1.3 mm(core only)
• 21 mW

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Constant Shift Discrepancy

• Incorrect for right-shift and negative values
  only
• Breaks the verification methodology
• Solved by creating a new primitive

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Disabled Clock Discrepancy

• State is updated but output is held when disabled
• Solved by specifying certain cycles as dont
  care

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Moving Beyond Cycle-Accuracy

• Using dont care windows could relax
  cycle-accuracy constraint
• Must be automated into verification process

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Conclusions

• Direct-Mapped hardware is the most efficient use
  of silicon
• Design with dataflow graphs, not sequential code
• Dont translate design data, refine it
• Verification methodology determines level of
  abstraction
• Chip-in-a-Day design flows are feasible