Adder Synthesis

1
VLSI(2) SW 2005
Adder Synthesis - with Synopsis Design Analyzer
Institute of Applied Microelectronics
Information Technology Kwang Yoal Kim
2
Adder Synthesis

• Synthesis
• The process of transforming a circuit described
  at a higher level
• of abstraction into a lower-level definition
• During this transformation, user-defined
  constraints define the
• goal of synthesis for the synthesis tools
• One important benefit is that the tools can
  evaluate several
• alternative implementations of the same
  circuit in order to get
• the best result, according to the specified
  constraints.

• Synthesis for Power Delay Product (PDP)
• Optimization by Synopsis Design Analyzer
• Change frequency for the first user-defined
  constraint to
• achieve the best PDP

3
Synthesis Report table

• Synthesis performed by a different frequency
  (constraint)
• Analyze the report Area, Power, Delay

4
Synthesis Result Chart 1.

• As frequency increased, Delay and Power
  respectively
• but PDP and area is not proportional to frequency

5
Synthesis Result Chart 2.

• As frequency increased, PDP is not increased
  proportionally
• PDP is relatively opposite to area

PDP and area comparison
AREA
6
Better Optimization

• Trade-off
• - Better optimization for PDP at cost of
  area.
• Power optimization can be combined with the
  constraints used for area optimization to achieve
  better power optimization
• Additional User-Defined Constraint
• Optimization can be done by various
  constraints (But since more the constraints, more
  care needs to be taken to see that there are no
  violations)
• - Combinational optimization
• logic-level
• gate-level
• - Sequential optimization
• - optional optimization
• flattening
• structuring