Design of 3D SiGe HBT Adders and Register Files

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Design of 3D SiGe HBT Adders and Register Files

• Okan Erdogan, Paul Belemjian, John Mayega, Daniel
  Prorok, Russell P. Kraft and John F. McDonald
• Rensselaer Polytechnic Institute

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Design Role on 3D Project

• Design Passive Test Structures for Yield and
  Via Resistance Chains
• Establish Performance Criteria and CAD Support
  for 3D Design
• Explore Applications for 3D with Demonstration
  Prototypes

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Design of 3D SiGe HBT Adders and Register
Files Okan Erdogan, Paul Belemjian, John Mayega,
Daniel Prorok, Russell P. Kraft and John F.
McDonald Rensselaer Polytechnic Institute The
role of the Design Team on 3D is to first provide
the artwork for a variety of test structures that
evaluate yield, via resistance, via size, and
other high frequency properties. However this
activity is also concerned with the design
methodologies and CAD tools for exploiting the
3D-chip medium. Additionally, several
demonstration design projects have been
undertaken with a view towards actually
experiencing the great breakthroughs provided by
3D technology, which permit higher performance at
lower power. One of these projects draws on the
groups traditional interest under past DARPA
sponsorship in design of fast RISC computing
engines. This Poster shows several aspects of
the development of these systems at clock rates
of 8/16/32 GHz using successive generations
(5HP/7HP/8HP) of IBMs SiGe HBT BiCMOS process.
This device technology provides device
performance comparable or better than that
predicted for end of road map CMOSonly
processes. So SiGe HBT devices provide a medium
with which one can explore the impact of
interconnections in those future systems with an
existing technology. As each generation of SiGe
HBT becomes available the impact of
interconnections on speed becomes increasingly
detrimental, and 3D provides a scheme for
removing the longest interconnections, revealing
the great speed of the underlying devices. Other
demonstration projects may include marrying
dissimilar wafer technologies such as DRAM and
SiGe.
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Via Chain Structure of Single Pillar Collett
Scheme
Bottom Layer
Via Layer
Collett Layer
Opening Layer
Pad Layer
Via Chains
Test Pads
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2 Layer 3D 8 GHz ClockComputer Demonstration
Project
Adder
Register File Banks
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Core Circuitry of an 8 GHz Computer
Finite State Machine
Decoders
Pipeline Registers
Cin
Pseudo-random bit generators
MUX/ Latch
Latch
Shift Registers
Adder
Cout
4 pipeline stages
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MUX
Comparators
Mem Modules
MUXes
Register File
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Adder block
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2D 3D Adder Delays

• Processing delays can be grouped into two types
  device delays and wiring delays
• Adding multiple wafer layers in 3D shortens wires
  and wiring delays but not device delays
• Progressive SiGe generations reduce device delays
  and result in slight reductions in wiring delays
  through shrinking device dimensions
• Comparisons of 1 layer (2D), 2 layer and 4 layer
  designs with the IBM 5HP, 7HP, and 8HP SiGe HBT
  processes show that significant delay reduction
  requires both 3D and faster processes

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2D 3D-2L/4L Adder Delays in IBM 5HP/7HP/8HP
SiGe HBT Process
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1-bit Memory Cell Schematic
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1-bit Memory Cell Layout
Bit Lines
Word Lines
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Register File Layout
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Inter-wafer 3D Vias in Finite State Machine
Inter-wafer 3D Via CAD Instance
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Summary/Conclusions

• The Computer Demonstration Project with SiGe HBT
  technology focusing on adder, register file and
  glue control /testing circuitry is a sufficient
  processor test vehicle for 3D.
• Circuit optimization in 3D, even for only 2
  layers, requires more design iteration than 2D
  optimization (particularly without 3D layout
  tools).
• Without 3D, wiring delay is projected to be 30
  of the total delay with the IBM 8HP SiGe process,
  which indicates that alternatives to 2D
  processors with an increasing number of
  interconnect levels are needed.

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Future Work

• 3D Design optimization is tied to process
  parameters
• Via size
• Process device size interconnect wire size
• Increasing the number of wafer layers will
  require a major change in the circuit layout to
  reduce wire lengths.
• Testing of fabricated circuits will determine
  appropriate changes for future iterations.
• Experience and successes will reduce the need for
  test circuitry and permit faster, more efficient
  designs.