Title: The Roadmap for Design and Design for Manufacturing Andrew B. Kahng, UC San Diego CSE
1The Roadmap for Design and Design for
Manufacturing Andrew B. Kahng, UC San Diego
CSE ECE DepartmentsChair, ITRS Design ITWG,
20012003ISMT Yield Council, September 25, 2003
2Outline
- The Design Roadmap
- DFM Symptoms, Problem, Solution
- DFM Futures Some Examples
3Design ITWG Contributions to ITRS
- System Drivers Chapter
- Defines IC products that drive manufacturing and
design technologies - ORTCs System Drivers framework for technology
requirements - Four System Driver classes
- SOC (Low-Power, High-Performance,
Mixed-Technology) - MPU
- Mixed-Signal
- Embedded Memory
- Design Chapter
- Design cost and productivity models
- Five technology areas design process / design
system architecture, system-level design,
logical/physical/circuit design, design
verification, design test - Cross-cutting challenges productivity, power,
manufacturing integration, interference,
error-tolerance - ORTC support
- Frequency, Power, Density models
4Big Picture
- Message Cost of Design threatens continuation
of the semiconductor roadmap - Design cost model
- Challenges are now Crises
- Strengthen bridge from semiconductors to
applications, software, architectures - Hertz and bits are not the same as efficiency and
utility - System Drivers chapter, with productivity and
power foci - Strengthen bridges among ITRS technologies
- Shared red bricks can be solved (or,
worked-around) more cost-effectively - Manufacturing Integration cross-cutting
challenge - Living ITRS framework to promote consistency
validation
5Design-Manufacturing Integration
- ITRS Design Chapter Manufacturing
Integration one of five Cross-Cutting
Challenges - Goal share red bricks with other ITRS
technologies - Lithography CD variability requirement ? new
Design techniques that can better handle
variability - Mask data volume requirement ? solved by
Design-Mfg interfaces and flows that pass
functional requirements, verification knowledge
to mask writing and inspection - ATE cost and speed red bricks ? solved by DFT,
BIST/BOST techniques for high-speed I/O, signal
integrity, analog/MS - Does X initiative have as much impact as copper?
6Living ITRS Framework
- Living roadmap internally consistent,
transparent models as basis of ITRS predictions
- ORTCs Models for layout density, system clock
speed, total system power in various drivers,
circuit fabrics - Visualization tool (at Sematech website) for
capture, exploration of ITRS models under
alternative scenarios - Is --- worth it?
7System Drivers Chapter
- Defines the IC products that drive manufacturing
and design technologies - Goal ORTCs System Drivers consistent
framework for technology requirements - Starts with macro picture
- Market drivers
- Convergence to SOC
- Main content System Drivers
- SOC focus on low-power PDA (and,
high-speed I/O) - MPU traditional processor core
- AM/S four basic circuits and Figures of Merit
- Embedded Memory eDRAM, eSRAM, eNVM (flash)
8MPU Driver
- Two MPU flavors
- Cost-performance (mobile) constant 140 mm2
die - High-performance (server/desktop) constant
310 mm2 die - Stake in ground 1 MPU organization multiple
cores, on-board L3 cache - More dedicated, less general-purpose logic
- More cores help power management (lower
frequency, lower Vdd, more parallelism ? overall
power savings) - Reuse of cores helps design productivity
- Redundancy helps yield and fault-tolerance
- MPU and SOC converge (organization and design
methodology) - Stake in ground 2 No more doubling of clock
frequency at each node
9FO4 INV Delays Per Clock Period
- FO4 INV inverter driving 4 identical inverters
(no interconnect) - Half of freq improvement has been from reduced
logic stages
10SOC Low-Power Driver Model (STRJ)
- SOC-LP PDA system
- Composition CPU cores, embedded cores,
SRAM/eDRAM - Requirements IO bandwidth, computational power,
GOPS/mW, die size - Drives PIDS/FEP LP device roadmap, Design power
management challenges, Design productivity
challenges
11Reqd Performance for Multi-Media Processing
GOPS
0.01
0.1
1
10
100
Video
MPEG1 Extraction
Compression
MPEG2 Extraction
MP/ML
MP/HL
MPEG4
JPEG
Audio Voice
Sentence Translation
Dolby-AC3
Voice Auto Translation
MPEG
Word Recognition
Graphics
3D Graphics
10Mpps
100Mpps
2D Graphics
Communication Recognition
SW Defined Radio
VoIP Modem
Face Recognition
Modem
Voice Print Recognition
Moving Picture Recognition
FAX
GOPS Giga Operations Per Second
12ANALOGY 1
- ITRS is like a car
- Before, two drivers (husband MPU, wife DRAM)
- The drivers looked mostly in the rear-view mirror
(destination Moores Law) - Many passengers in the car (ASIC, SOC, Analog,
Mobile, Low-Power, Networking/Wireless, )
wanted to go different places - Starting in 2001 ITRS (System Drivers Chapter)
- Some passengers became drivers
- All drivers explain more clearly where they are
going
13Design Challenges - Silicon
- Silicon Complexity impact of process scaling,
new materials, new device/interconnect
architectures - Non-ideal scaling (leakage, power management,
circuit/device innovation, current delivery) - Coupled high-frequency devices and interconnects
(signal integrity analysis and management) - Manufacturing variability (library
characterization, analog and digital circuit
performance, error-tolerant design, layout
reusability, static performance verification
methodology/tools) - Scaling of global interconnect performance
(communication, synchronization) - Decreased reliability (SEU, gate insulator
tunneling and breakdown, joule heating and
electromigration) - Complexity of manufacturing handoff (reticle
enhancement and mask writing/inspection flow,
manufacturing NRE cost)
14Design Challenges - System
- System Complexity exponentially increasing
transistor counts, with increased diversity
(mixed-signal SOC, ) - Reuse (hierarchical design support, heterogeneous
SOC integration, reuse of verification/test/IP) - Verification and test (specification capture,
design for verifiability, verification reuse,
system-level and software verification, AMS
self-test, noise-delay fault tests, test reuse) - Cost-driven design optimization (manufacturing
cost modeling and analysis, quality metrics,
die-package co-optimization, ) - Embedded software design (platform-based system
design methodologies, software verification/analys
is, codesign w/HW) - Reliable implementation platforms (predictable
chip implementation onto multiple fabrics,
higher-level handoff) - Design process management (team size / geog
distribution, data mgmt, collaborative design,
process improvement)
15Design Chapter Outline
- Introduction
- Scope of design technology
- Complexities (silicon, system)
- Design Cross-Cutting Challenges
- Productivity
- Power
- Manufacturing Integration
- Interference
- Error-Tolerance
- Details of five traditional technology areas
Design Process, System-Level, Logical/Physical/Cir
cuit, Functional Verification, Test - Key 2003 changes
- Increased analog and circuits content
- Refinement of design cost metrics
- Design system architecture and flow
- SEU and reliability
16Design Technology Crises
Incremental Cost Per Transistor
Test
Manufacturing
Manufacturing
SW Design
NRE Cost
Turnaround Time
Verification
HW Design
- 2-3X more verification engineers than designers
on microprocessor teams - Software 80 of system development cost (and
Analog design hasnt scaled) - Design NRE gt 10s of M ?? manufacturing NRE 1M
- Design TAT months or years ?? manufacturing TAT
weeks - Without DFT, test cost per transistor grows
exponentially relative to mfg cost
17Design Cost Model
- Engineer cost per year increases 5 / year
(181,568 in 1990) - EDA tool cost per year (per engineer) increases
3.9 per year - Productivity due to 8 major Design Technology
innovations - RTL methodology
-
- Large-block reuse
- IC implementation suite
- Intelligent testbench
- Electronic System-level methodology
- Matched up against SOC-LP PDA content
- SOC-LP PDA design cost 15M in 2001
- Would have been 342M without EDA innovations
18Design Cost of SOC-LP PDA Driver
19Cross-Cutting Challenge Productivity
- Overall design productivity of normalized
functions on chip must scale at 4x per node for
SOC Driver - Reuse (including migration) of design,
verification and test effort must scale at gt
4x/node - Analog and mixed-signal synthesis, verification
and test - Embedded software productivity
20Cross-Cutting Challenge Power
- Reliability and performance analysis impacts
- Accelerated lifetime testing (burn-in) paradigm
fails - Large power management gaps (standby power for
low-power SOC dynamic power for MPU) - Power optimizations must simultaneously and fully
exploit many degrees of freedom (multi-Vt,
multi-Tox, multi-Vdd in core) while guiding
architecture, OS and software
21Cross-Cutting Challenge Interference
- Lower noise headroom especially in low-power
devices - Coupled interconnects
- Supply voltage IR drop and ground bounce
- Thermal impact on device off-currents and
interconnect resistivities - Mutual inductance
- Substrate coupling
- Single-event (alpha particle) upset
- Increased use of dynamic logic families
- Modeling, analysis and estimation at all levels
of design
22Cross-Cutting Challenge Error-Tolerance
- Relaxing 100 correctness requirement may reduce
manufacturing, verification, test costs - Both transient and permanent failures of signals,
logic values, devices, interconnects - Novel techniques adaptive and self-correcting /
self-repairing circuits, use of on-chip
reconfigurability
23Challenge Manufacturing Integration
- Goal share red bricks with other ITRS
technologies - Lithography CD variability requirement ? new
Design techniques that can better handle
variability ? - Mask data volume requirement ? new Design-Mfg
interfaces and flows that pass functional
requirements, verification knowledge to mask
writing and inspection ? - ATE cost and speed red bricks ? new DFT,
BIST/BOST techniques for high-speed I/O, signal
integrity, analog/MS ? - Can technology development reflect ROI (value /
cost) analysis Who should solve a given red
brick? - Shared Red Bricks
24Example Manufacturing Test
- High-speed interfaces (networking, memory I/O)
- Frequencies on same scale as overall tester
timing accuracy - Heterogeneous SOC design
- Test reuse
- Integration of distinct test technologies within
single device - Analog/mixed-signal test
- Reliability screens failing
- Burn-in screening not practical with lower Vdd,
higher power budgets ? overkill impact on yield - Design Challenges DFT, BIST
- Analog/mixed-signal
- Signal integrity and advanced fault models
- BIST for single-event upsets (in logic as well as
memory) - Reliability-related fault tolerance
25Example Lithography
- 10 CD uniformity requirement causes red bricks
- 10 lt 1 atomic monolayer at end of ITRS
- This year Lithography, PIDS, FEP agreed to
relax CD uniformity requirement (but we still see
red bricks) - Design challenge Design for variability
- Novel circuit topologies
- Circuit optimization (conflict between slack
minimization and guardbanding of quadratically
increasing delay sensitivity) - Centering and design for /wafer
- Design challenge Design for when devices,
interconnects no longer 100 guaranteed correct - Can this save in manufacturing, verification,
test costs?
26ANALOGY 2
- ITRS technologies are the parts of the ITRS car
- Every one takes the engine point of view when
it defines its requirements - Why, you may take the most gallant sailor, the
most intrepid airman, the most audacious soldier,
put them at a table together what do you get?
The sum of their fears. - Winston Churchill
(quoted by Paolo Gargini) - But, all parts must work together to make the car
go smoothly - Need global optimization of requirements
- ? Shared Red Bricks
27Outline
- The Design Roadmap
- DFM Symptoms, Problem, Solution
- DFM Futures Some Examples
28Symptoms Routing Rules (1)
- Minimum area rules and via stacking
- Stacking vias through multiple layers can cause
minimum area violations (alignment tolerances,
etc.) - Via cells can be created that have more metal
than minimum via overlap (used for intermediate
layers in stacked vias) - Multiple-cut vias
- Use multiple-cut vias cells to increase yield and
reliability - Can be required for wires of certain widths
- Multiple via cut patterns have different spacing
rules - Four cuts in quadrilateral five cuts in cross
six cuts in 2x3 array - With wide-wire spacing rules, complicates pin
access - Cut-to-cut spacing rules ? check both cut-to-cut
and metal-to-metal when considering via-to-via
spacing - Line-end extensions
- Vias or line ends need additional metal overlap
(0th-order OPC)
29Symptoms Routing Rules (2)
- Width- and Length-dependent spacing rules
- Width-dependent rules domino effects
- Variant parallel-run rule (longer parallel
runs ? more spacing) - Measuring length and width halo rules affect
computation - Influence rules or stub rules
- A fat wire, e.g., power/ground net, will
influence the spacing rule within its
surroundings ? any wire that is X um away from
the fat wire needs to be at least Y um away from
any other geometry. - Example fat wire with thin tributaries
- bigger spacing around every wire within certain
distance of the thin tributaries - ECO insertion of a tributary causes complications
- Strange jogs and spreading when wires enter an
influenced area
30Example LEF/DEF 5.5, April 2003
31Example LEF/DEF 5.5, April 2003
32Symptoms Routing Rules (3)
- Density
- Grounded metal fills (dummy fill)
- Via isodensity rules and via farm rules (via
layers must be filled and slotted, have
width-dependent spacing rule analogs, etc.) - Non-rectilinear (?-geometry) routing
- X-Architecture http//www.xinitiative.org/
- Y-Architecture http//vlsicad.ucsd.edu/Yarchitec
ture/ , LSI Logic patents - Landing pad shapes (isothetic rectangle vs.
octagon vs. circle), different spacings (1.1x)
between diagonal and Manhattan wires, etc. - More exceptions
- More non-default classes (timing, EM reliability,
) - Not just power and clock
- gt0.25um width may be wide ? many exceptions
33Symptoms Routing Rules
- Degrade completion rates, runtime efficiency
- Postprocessing likely no longer suffices
- E.g., antennas
- There is no chip until the router is done
- Must / Should / Can tomorrows IC routers
independently address these issues?
34Whose Job Is It To Solve
- Mask NRE cost (? runtimes ? shapes
complexity) - BEOL catastrophic yield loss
- Deposited copper ? can infer yield loss
mechanisms - Open faults more prevalent than short or bridging
faults - High-resistance via faults
- Cf. non-tree routing for reliability and yield?
- Variability budget for planarization
- Copper is soft ? dual-material polish mechanisms
- Oxide erosion and copper dishing ?
cross-sectional variability, inter-layer bridging
faults, - Low-k thermal properties, anisotropy,
nonuniformity - Resistivity at small conductor dimensions
35The Problem Evolution
- Conflicting goals
- Designer freedom, reuse, migration
- EDA maintenance mode
- Process/foundry enhance perceived value
( add rules) - ? Prisoners Dilemma who will invest in change?
- Fiddling Incremental, linear extrapolation of
current trajectory - GDS-3
- Thin post-processing layers (decompaction, RET
insertion, ) - Leads to dark future (12th Japan DA Show
keynote)
36DAC-2003 Nanometer Futures PanelWhere should
extra RD be spent?
37The Solution Co-Evolution
- Designer, EDA, and process communities cooperate
and co-evolve to maintain the cost (value)
trajectory of Moores Law - Must escape Prisoners Dilemma
- Must be financially viable
- At 90nm to 65nm transition, this is a matter of
survival for the worldwide semiconductor industry - Example Focus Areas
- Explicit manufacturability and cost/value
optimization - Restricted layout
- Intelligent mask data prep
- Analog (not binary) rules
- (Many layout and design optimizations)
- Disclaimer Not a complete listing
38Foundation of the (DFM) Solution
- Bidirectional design-manufacturing data pipe
- Fundamental drivers cost, value
- Pass functional intent to manufacturing flow
- Example RET for predictable timing slack,
leakage, yield - RETs should win , reduce performance variation
- ? cost-driven, parametric yield constrained RET
- Pass limits of manufacturing flow up to design
- Example avoid corrections that cannot be
manufactured or verified ? e.g., design should be
aware of metrology - N.B. 1998-2003 papers/tutorials
http//vlsicad.ucsd.edu/abk/TALKS/
39Outline
- The Design Roadmap
- DFM Symptoms, Problem, Solution
- DFM Futures Some Examples
401 Design for Value
- Mask cost trend ? Design for Value (DFV)
- Design for Value Problem
- Given
- Performance measure f
- Value function v(f)
- Selling points fi corresponding to various values
of f - Yield function y(f)
- Maximize Total Design Value ?i y(fi)v(fi)
- or, Minimize Total Cost
- Probabilistic optimization regime
- See "Design Sensitivities to Variability
Extrapolation and Assessments in Nanometer VLSI",
IEEE ASIC/SoC Conference, September 2002, pp.
411-415.
41Obvious Step Function-Aware OPC
- Annotate features with required amount of OPC
- E.g., why correct dummy fill?
- Determined by design properties such as setup and
hold timing slacks, parametric yield criticality
of devices and features - Reduce total OPC inserted (e.g., SRAF usage)
- Decreased physical verification runtime, data
volume - Decreased mask cost resulting from fewer features
- Supported in data formats (OASIS, IBM GL-I,
OA/UDM) - Design through mask tools need to make, use
annotations - (General RET trajectory rules ? models ?
libraries!)
42MinCorr Minimum Mask Complexity
- Levels of RET Levels of CD control
-
- Levels of RET levels of CD control
Type of OPC Ldrawn (nm) 3? of Ldrawn Figure Count Delay (?, ?) for NAND2X1
Aggressive 130 5 5X (60.7, 7.03)
Medium 130 6.5 4X (60.7, 7.47)
No OPC 130 10 1X (60.7, 8.79)
OPC solutions due to K. Wampler, MaskTools,
March 2003
CD studies due to D. Pramanik, Numerical
Technologies, December 2002
43MinCorr Methodology (DAC-03)
- Mapping of area minimization to RET cost
optimization - Yield library analogous to timing libraries
(e.g., .lib) - ? Off-the-shelf synthesis tool performs OPC
sizing - Up to 79 reduction in figure complexity without
any parametric yield impact
Gate Sizing ? MinCorr
Cell Area ? Cost of correction
Nominal Delay ? Delay (?k?)
Cycle Time ? Selling point delay
Die Area ? Total cost of OPC
442 Process-Aware Design
- Anisotropy in H vs. V bias
- Features in one direction (scanning, raster
write, ) may be better controllable than those
in the orthogonal direction - Single orientation throughout layout is preferred
- Dominant (critical-feature) orientation in layout
design should match write direction - Wafer symmetries (e.g., etch gradient due to
spin-on) - Iso-Dense balancing (imaging through focus)
453 Intelligent MDPWrite
- MDP driven by (write error MEEF) wafer CD
error - Partitioning into multiple gray-scale writing
passes - Apertures, beam currents, dwell times, shot
ordering, - EDA tools define stripe, major field, subfield
boundaries! - Electrical / functional defect criteria
464 Mask Write Optimizations
- Conflicting goals resolution, CD control,
throughput - Resist heating large contributor to mask CD
variation - Knobs beam current, flash size, idle times,
grayscale passes - Subfield writing order example new knob
- Reduced heating ? increased beam current density
- Reduced dwell time compensates for travel and
settling time
1 2 3 4
8 7 6 5
9 10 11 12
16 15 14 13
1 13 5 9
6 10 2 14
3 15 7 11
8 12 4 16
Ordering 1
Ordering 2
- Ordering 2 is self-avoiding ? lower pre-flash
temps
47Self-Avoiding Subfield Order for Mask Write
- SPIE Microlithography 03, Photomask Japan 03
- Simulation of subfield temperatures within a main
deflection field for sequential vs. greedily
optimized writing schedules
Max 32.68?C Mean 16.07?C
Greedily optimized schedule
485 Fill Parametric Yield Impact
- Performance Impact Limited Fill (PIL-Fill),
DAC-2003 - Fill adds capacitance, hurts timing and SI
closure - Plain capacitance minimization objective is not
sufficient - CMP modeling ? layout density vs. dimensions
built into RLCX
1
top view
Active lines
2
B
A
C
Active lines
3
w
fill grid pitch
D
E
4
5
buffer distance
F
G
6
49Min-Slack, Fill-Constrained PIL-Fill
- Inputs LEF/DEF, extracted RSPF, STA (slack)
report - Drive ILP and greedy PIL-Fill methods by
estimated lateral coupling and Elmore delay
impact - Baseline comparison LP/Monte-Carlo methods
- Iterated greedy method for MSFC PIL-Fill reduces
timing slack impact of fill by 80 (average over
all nets), 63 (worst net)
506 Analog Rules
- We dont need no ((! rules
- Rules just make lithographers feel better (?)
- Ultimately, bottom line is cost of ownership,
TCOG - Given adequate models of MDP, RET and Litho
flows, design tools can and should optimize
parametric yield, /wafer, profits - More examples critical-area reduction by
decompaction, introducing redundancy (vias,
wires), - Automated learning of models and implicit rules
- Current approach test wafers, test structures,
second-hand understanding - Future machine learning techniques
517 Restricted Layout
- Soft reset 1-time hit on Moores Law density
scaling - Restricted Design Rules (RDR) can be
compensated many ways - embedded 1-T SRAM fabric, stacking, I/O circuit
design, - N.B. Moores Law is a meta Law!
Dual Exposure Result
Islands
Checkerboard
Example PhasePhirst! (Levenson et al.)
0?
180?
Transparent
Opaque
Trim Mask Exposure
First Exposure
Dark-Field PSMs
or
M. D. Levenson, 2003
52Pre-Made Mask Blanks
- PhasePhirst!
- Levenson/Petersen/Gerold/Mack, BACUS-2000
- Idea mask blanks can be mass-produced and stored
to reduce average cost (e.g., 10K), then
customized on demand
M. D. Levenson, 2003
53Notes on Regular Layout
- 65 nm has high likelihood for layouts to look
like regular gratings - Uniform pitch and width on metal as well as poly
layers - ? Predictable layouts even in presence of focus
and dose variations - More manufacturable cell libraries with regular
structures - New layout challenges (e.g., preserving
regularity in placement) - Caveats
- Non-minimum width poly is less susceptible to
variation ? larger devices (with same W/L) may
lead to more robust designs (so, selective
upsizing may be an alternative to regular
layouts) - 180nm node is a sweet spot for cost,
analog/mixed-signal integration, etc. ? more and
more technology nodes will tend to coexist
547 Charging and Antennas
- Process steps use plasmas, charged particles
- Electrical fields over gate oxides induce damage
(Vt shift) or breakdown - Limit antenna ratio (Apoly AM1 ) /
Agate-ox - AMx metal(x) area that is electrically
connected to node without using metal (x1), and
not connected to an active area - Bridging (break antenna by hopping to higher
layer) - Extra wiring, vias, congestion
- Reverse-biased diode or source-drain contact near
gate - Leakage, area, timing penalties
- Will antenna ratios continue to decrease?
- High-k gate dielectrics ? increased physical Tox
? less leaky, hard failure modes? - More preemption (no post-processing, or dioded
cells)? - Tradeoff unfixed antenna yield penalty for fixed
antenna yield loss?
558 Pattern Collapse
- Pr(pattern collapse) f(length)
- ? Length-dependent spacing rules
- Limits wire AR, packing density
- Standardized embedding of long wires for
manufacturability and physical reliability - becomes
- ???
Cao et al. U. Wisconson
569 Data Compression
- Today RET complexity ? exploding data volume
- Partitioning of compression and decompression?
- Equipment architecture question where to put
engines, I/Fs, storage? - Largely orthogonal to design considerations
- Procedural compression largely unexplored? (Ex
Verilog SPR binaries runscripts
representation of detail-routed layout) - Design for compressibility? (DATE 03, SPIE ML
03) - What is ROI of relaxing constraints on layout? Of
k bytes of data? - How context-sensitive must patterning be?
(Lessons from RET) - Use of lossy compression? (SPIE ML 03)
- What design features can be lost? (Ex dummy
fill)
57Choice of Geometric Compression Operators
- Who is using compression, at what stages of
design-mfg flow? - Is there synergy between manufacturing
flow and
GDSII-OASIS-UDM?
OASIS Format (recent SEMI standard) defines eight
repetition types. A repetition represents an
array of (polygon) records, enabling
compression of layout data.
equivalent to GDSII AREF
Other OASIS repetition types
5810 Leakage Management
- Huge parametric yield loss
- Subthreshold leakage current varies exponentially
with threshold voltage I ? exp(-Vth) - Vth f(channel length, oxide thickness, doping)
- Most affected by variations in gate length
100 Isub
10 Ld
Dennis Sylvester, U. Michigan
59Leakage Understanding Control
- Understanding variation in chip-level leakage
due to intra- and inter-die Leff variation - cost-benefit of controlling relevant variation
sources - Control Multi-everything (threshold, supply,
sizing) - New control can use selective Lgate bias (2 nm)
to reduce leakage by 60 with no loss in critical
path delay - Draft in preparation
60Conclusions
- Designer, EDA, and mask communities must
co-evolve to maintain the cost (value) trajectory
of Moores Law - Wakeup call Intel 157nm announcement
- Basic goal bidirectional design-mfg data pipe
- Drivers cost, value
- Pass functional intent to mask and foundry flows
- Pass limits of mask and foundry flows up to
design - Several examples given
- Manufacturability and cost/value optimization
- Leakage power
- Restricted layout
- Intelligent mask data prep
- Analog rules
- Please pay someone to do this!
61THANK YOU !