DECCompaqHP Alpha

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DEC/Compaq/HP Alpha
Processor http//www.pckurier.pl/archiwum/artykul
y/kowalski_marek/1998_12_66/alpha.jpg Server
http//www.hp.com/hpinfo/newsroom/press_kits/2003/
alpha/bigGS1280_32way_DO.jpg
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Presentation Summary

• Historical background
• Instruction set architecture
• Hardware architecture
• Pipeline
• Cache
• Benchmarks

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WHY THE ALPHA FAILED

• MILESTONES
• 1991 - Apple
• 1994 Mounting Losses
• 1995 EV5
• 1998 Samsung and Compaq
• 2001 HP
• April 27, 2007

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Memory Addressing
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Data Types
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Floating Point Data Types
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Instruction Format
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Alpha 21264 Hardware Architecture Overview

• Boxes
• Ibox
• Ebox
• Fbox
• Mbox
• Cbox
• On-Chip Caches
• Icache
• Dcache

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Alpha 21264 Pipeline

• Seven-stage pipeline
• 0) Instruction Fetch
• 1) Instruction Slot
• 2) Map
• 3) Issue
• 4) Register Read
• 5) Execute
• 6) Dcache Access

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Pipeline abort penalties

• JSR Jump to subroutine
• HW_RET Return from exception or interrupt
• DTB Data Translation Buffer
• ITB Instruction Translation Buffer

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Cache

• Primary Cache
• Arrangement
• Size
• Performance

• Secondary Cache
• Location
• Size
• Components

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Cache Coherency

• Icache and Dcache Coherency
• Bcache Coherency
• Locked Blocks
• Coherency Protocols

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Cache Subset Hierarchy
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External Ports

• External Cache and System Interface (Cbox)
• Victim address file
• Victim data file
• Duplicate tag array
• Memory Reference Unit (Mbox)
• Load queue
• Store queue
• Miss address file

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Sample Load Instruction

• Mbox operations
• Hit?
• Miss?
• Cbox operations

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SPEC 95 Benchmarks (Integer and Floating Point)
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Goodbye, Alpha