IT Session Summary

1
IT Session Summary

• New Proposals and State of the Art towards a KM3
  project design.

2
General layout
Information distribution
photon detection
detector
Information transmission
Information management
3
Photon detection

• Position
• Resolution 10 cm
• Time
• Resolution 1 ns
• Charge
• Two-photon purity gt99
• Dynamic range 10-20

4
Detector operation

• Number of PMTs
• N 10,000
• Singles rate
• f 30-100 kHz
• Data size
• v 6 Byte / hit

5
Information management

• I/O data rates
• Operation
• Remote
• Multi-user
• Event
• Definition
• Efficiency
• Purity

6
Functional geography

• Photon detection
• High data rate
• Uni-directional
• Low information density
• Timing ns

• Instrumentation
• Low data rate
• Bi-directional
• High information density
• Timing ms

Separation of functionalities
7
Photon counting

• Large PMT
• Slow
• Analogue
• Q-integrator
• ADC

• Small PMT
• Fast
• Digital
• single photon counting
• Time-over-threshold

Two-photon purity
8
Example off-shore TDC
complex off-shore electronics
9
Example on-shore TDC

• Protocol
• DWDM (l,fiber)
• TDC
• auto-calibration
• multi-threshold (waveform)

No off-shore electronics
10
Directional information (2)

• Causality relation is more strict
• Reduction of random triggers
• A priori selection of data frames
• Use predefined set of directions
• Exclude (or down-scale) downward going muons

11
voltage divider considerations

• Requirement
• establish maintain a set of fixed dynode
  potentials
• Two types available
• resistor type
• active divider (FET)
• The all-resistor divider always fails the
  requirement but why and how
• badly?

12
solutions

• increase ID0 by decreasing all R values
• or
• reduce R(dn-a) only
• use either a fully or partially active divider
  based on emitter follower action
• capacitors for pulsed signals

13
(No Transcript)
14
Readout State of the Art
Large Area PMTs
Waveform Digitizers

• ASIC
• Analog Memories
• Charge integrators
• Slow Digital ADCs

• FPGA based readout
• Fast Digital ADCs

15

• SYSTEM REQUIREMENTS
• Very low power because of the distance from the
  shore
• Flexibility to give the possibility of changing
  parameters
• Very small dead-time to get a good detector
  efficiency
• High dynamic range to fit with different kinds of
  experiments
• Very good accuracy of experimental data
• Low cost, if possible!

16
Possible uses in physics experiments.

• ANALOG TRANSIENT RECORDER time expender.
• Analog delay line (need a readout as fast as the
  write operation).
• Level 1 buffer or filter in HEP experiments.

CK40 MHz
Préampli. filter
Write
DAQ
Analog Pipeline
ADC
Selective readout of a given Number of cells
Lv 1 trigge (1.5µs latency)
17
The beginning of the history
- L1 Buffer of ATLAS LARG calorimeter -
Simultaneous Write/read  dead-time free . -12
channels of 144 cells - Analog multiplexing
toward a 5MHz ADC - RADHARD (technologie DMILL,
CMOS 0.8). - Fsample 40 MHz, BW 50 MHz. -
Dynamique range (300µV/4V) gt 13 bits (world
record). - 80000 chips manufactured, tested and
delivered.
-Start of RD (RD3 in 94). -Final design in
97. -Production of 80000 chips in
2001-2002. -Tests in 2002-2003. -Delivery in
2004.
18
The ARS0 chip initially designed for ANTARES

• Gsample/s time expander chip originally developed
  for the ANTARES experiment.
• Based on sampling-DLL technique
• 5 channels /chip, 128 cells per channel.
• Sampling _at_ 1 GHz
• Readout 1 MHz/sample triggered by an external
  signal
• A programmable number of cells is read
• starting from a programmable offset from the
  trigger
• Low power (500mW).
• 8-9 bits dynamic range

AMS CMOS 0.8µm
Heart of the ARS1 chip for ANTARES Used _at_ CEBAF
by IN2P3/LPC Used by HESS I
19
PIPELINE The Heart of a hand-held oscilloscope

• PIPELINE is a system on chip including a similar
  SCA designed by us.
• Includes 250000 transistors.
• Heart of a hand held oscilloscope developed by
  CHAUVIN-ARNOUX METRIX
• Its Front-end uses very few other components than
  PIPELINE.

1GS/S 100MHz BW Up to 4 floating input
channels with 600V insulation
20
The SAM chip block diagram
60000 transistors. 11 mm2
Need very few external signals to work (ltgt from
MATACQ). Many modes configurable by slow-control
(special modes, testability). Includes a TDC with
LSB1/Fsample Auto-configuration _at_ power on
21
The ARS in the Local Control Module
3 ARS board

• DAQ Board
• FPGA 106 gates
• VxWorks
• 100 Mbit/s

Clock board (50 ns)
Compass, tiltmeter
Power supply
Ethernet 100 Mbit/s ? 1 Gbit/s, hydrophon..
22
The ARS chip requirementss

• First Level Functionalities
• Discriminate signals coming from the PMT.
• Measure their time (0.5 ns rms precision).
• Measure their charge.
• Bufferize and Derandomize the event flow.
• Convert charge time in digital data.
• Format the events serialize them toward the DAQ
  board.
• Oscilloscope mode.
• 2nd Level Functionalities
• Rate Monitor rate alarm.
• Filter by L1 and L2 (historical reason).
• Test Led generator.
• All this for a reasonable power consumption and a
  low cost.

23
The ARS chip layout
AMS CMOS0.8µm technology. 70000 transistors. 23
mm2 Packaged in QFP100 package
Produced in 2004 on one of the last batch of the
technology.
Needs 5 protoyping before production
The ARS chip a mixed-mode analog digital system
on chip
24
If we had to redesign the ARS some thoughts
about the design architecture

• Too complicated design
• 5 functions timing, integrator,waveform anode
  and dynode, and FIFO could be probably done by an
  unique block (a single high dynamic range SCA
  with two modes of read-out).
• The Token ring adds some complexity all should
  be done in one chip. The threshold must me
  equilibrated to equalize the rate
• Too many  parasitic  functions (counting rate
  monitor) gt could be done elsewhere with a
  dedicated data flow.
• Interest of data formatting and full readout
  control inside the chip ? gt In my opinion, the
  ARS is too clever it should be a pure slave
  driven by an external controller.
• Should the ADC be integrated in the chip ?
• The more the chip is complex, the more the test
  (and qualification) is hard.
• Too many pins connected to the input signal (pb
  for impedance matching).
• Too many external components External references
  ARSconv external data synchronizer could be
  avoided (by a better chip design).

25
Est. Reset
FIFO
FIFO
16/
R
16/
16 Bit
O
I
O
I
Counter
Counter
Load
Load
Read
Read
20 MHz
CkI
CkI
RFf
RTc
RFf
RTc
TS
TS
TSPC
TSPC
RAdc
RAdc
NSPE
NSPE
NSPE
NSPE
Control Unit
Control Unit
Vi
Start
Start
Vi
Start
Start
ACk
ACk
Dyn
Dyn
Dyn
Dyn
PwD
PwD
CR
CR
R/W
R2
S
SE1
SE2
R1
CkO
R/W
R2
S
SE1
SE2
R1
CkO
200 MHz
PLL
PLL
Ck
PwD
Ck
PwD
DPTU
ADC
ADC
SE
CkW
CkR
R/W
R
Cs
SR
SE
CkW
CkR
R/W
R
Cs
SR
10/
LIRA
LIRA
I0
Os
Data Pack
I0
Os
Data Pack
O
O
I
I
ADS 901
ADS 901


I1
I1
80ns
Anode
Ot
Ot
Transfer U.
Transfer U.
I2
I2
3x250 channel SCA
3x250 channel SCA
5 Mbit/s
80ns
Dynode
PM
CkW
CkR
R/W
Cs
CkW
CkR
R/W
Cs
SE
R
SR
SE
R
SR
LIRA
LIRA
Os
Os
I0
I0
I1
I1
Ot
Ot
I2
I2
3x250 channel SCA
3x250 channel SCA
on chip on LIRA board
26

• Considerations on chip LIRA05 and CU FPGA
• Not Uniform Gain and Offset over all channels -gt
  CALIBRATION
• Input Bandwidth 33 MHz _at_ -3 dB
• Linear range Over 1,5 V Resolution 3.5 mV rms
  8-9 bit
• TSPC tested ok
• PLL 200 MHz tested ok
• Slow Control Interface tested ok
• Power Dissipation of the whole chip (write
  read 256 cells) lt 200 mW
• FPGA Interfacing tested ok
• Possible OM Test -gt new Board

27
LIRA06 Sampling

• 3 sampling modes
• LIRASHORT
• 4 independent memory banks sampling _at_ START
  (TSPC)
• 3 channels 10 cells
• 200 MHz sampling 20 MHz transfer
• Serial transfer towards ADC
• LIRALONG
• TSPC enabled signal over Threshold more than 50
  ns
• 3 channels 200 cells
• 200 MHz sampling 20 MHz transfer
• Serial transfer towards ADC
• FADC
• TSPC enabled signal over Threshold more than 1
  ms
• Integrated signal
• 10 bit 20 MHz Flash ADC
• 1 Ksample record length

28
50 ns lt PMT Signal width 50 ns lt 1ms
Signal over threshold after 50 ns
Anode20
Anode4
Anode0,44
50 ns
1 ms
Write 200 MHz
Read 20 MHz
First 50 ns LiraShort Timestamp
10 50 ns 500ns lt 200 ms
10 bit
10 5 ns 50 ns
20 bit Time stamp
Anode20
Anode4
Anode0,44
29
PMT Signal Path L0T and FIFO

• The Level Zero Trigger
• performs the zero skipping (actually a noise
  level skipping) but can be used to reduce the
  data rate, if necessary, by increasing the level
  threshold, at the cost of loosing the lower
  energy signals
• Some pretrigger samples can be stored as well as
  some underthreshold samples after the event
• The FIFO
• 2048 samples (organized in slots of 4 samples
  each)
• Receives short bursts from and its data are
  exctracted with a fixed rate (if not empty)
• Dead time probability (with a 50kHz Poisson rate,
  a 50ns event length) is negligible (not
  considering non poissonian phenomenon, like
  bioluminescence)
• Timing
• Threshold time and time register wrap events are
  put into the FIFO
• Synchronicity between time register wrap events
  and time register reset received from the FCM,
  allows a control over the integrity of the timing
  information at the FEM level

30
PMT Signal Path AFE

• The calibration circuit feeds the compressor with
  a well known current (12 bit precision)
• The calibration curve allows to map the PMT
  current to the ADC channel
• By inverting this relation, the PMT current can
  be knows as a function of the ADC channel

A1
A2
AC
31
Results sampled waveform

• Digital Oscilloscope and decompressed data

32
Connectors

• J1 PMT Input
• J2 Gate
• J3 HVPSU Connector
• Vcc Gnd
• Control voltage (0 2.4V)
• Feedback Voltage (0 2.5V)
• HVPwm (CMOS out)
• User Programable Output (CMOS out)
• J5 User Connector
• Analog Input (0 2.5V)
• Analog Output (0 2.4V)
• Gnd
• J9 RS232
• J10 FCM Connector

J10
J11
J9
J2
J3
J1
J5
10 cm
33
FEM0
FEM1
The Single Subsystem a Hardware-oriented point
of view
Optical Module data come from 4 (up to 8) Front
End Modules (FEM from now on)
Off-shore floor data concentration is carried out
by a Floor Control Module (FCM from now on)
FEM2
FEM3
One floor data is received on-shore by a twin FCM
board, plugged on a host machine (FCM Interface,
or simply FCMI in the following)
At the FCMI, data are made available on memory
buffers (Front End Buffers, or FEBs). Each FEB
contains formatted data issued from the
corresponding Front End Module
FCMI
34
Information links analisys. Link 2 FCM
Off-shore? FCM On-shore
Physical medium totally passive Fiber Optics link
Prodocol STM-1 (part of SDH standard)
Existing Stardardized TLC Self-Synchronous Serial
Protocol
Main features
Transmission organized in frames, used here as
simple data containers
Frame clock
8 kHz 19.44 MHz 155.52 MHz
Byte clock
bit clock
35
Simplified version of a fiber network for a NEMO
tower
Main simplifications
- Information flow is only upwards (only sensor
data are considered)
- Only four floors per tower (floor 3/0 relative
power loss due to ADD devices negligible)
FCM 3
- No redundancy need accounted
Floor 3
FCM 2
Floor 2
FCM 1
Floor 1
Floor 0
FCM 0
36
DWDM System certfication at italian ISCTI
(Ministry of TLC - July 2005)
SDH Protocol Analyzer
DWDM Transceivers
155 Mbps eye diagram
On-Shore Off-Shore FCM Boards
Add Drop Modules
Real test fiber link over ?100 km ? bit error
rate lt 10-9
37
Overview

• Platform FPGAs
• Xilinx Virtex-II Pro devices
• Typical SoC Architecture
• Example designs (On-going projects)
• Test bench for the ANTARES off-shore DAQ/SC board
• Selective Read-out Processor (SRP) for the CMS
  ECAL
• On-board Gamma Ray Burst DAQ/Trigger and alert
  system for the ECLAIRs microsatellite
• Conclusive remarks on the use of SoC approach

38
Prototyping and design

• Number of development kits with various Virtex-II
  Pro devices
• 2VP7, 2VP30, 2VP50
• 1 or 2 PowerPCs
• 4 or 8 RocketIO transceivers
• Pluggable optical modules
• LVDS interfaces
• RS232, Ethernet
• 64 Mbyte external memory
• P160 extension module
• RS232 Ethernet Flash Memory
• Soft IP cores
• Software libraries

FF1152 development kit from Memec Inc.
39
SoC example
50 MHz
50 MHz
RS232 console19200 baud
PowerPC100 MHz
User Logic
Reset IDregister
32 kB memory
P L B
O P B
Dataregister
256 bytememory
PLB / OPBbridge
Slaveinterface IPIF
IPIC
32-bit R/W
Clock, Reset, JTAG

• 12 of BRAM and 7 of logic cells of a middle
  range 2VP30 device
• Plenty resources for much more sophisticated user
  cores

40
1st SoC development example Test bench for the
ANTARES DAQ/SC board

• Production test bench for 350 Local Control
  Modules
• Electronics to be installed in Mediterranean Sea
  2.5 km below surface
• Fully automated with test report populating
  quality control DB
• Several data control interfaces with different
  IO standards

• Test bench emulates LCM environment
• Stimulates inputs and analyzes responses

41
The test bench

• SoC-based tester board
• ?Memec development kit with Xilinx 2VP30 FPGA
• ?Supports hot swappable DAQ/SC
• ?Test duration 15 minutes per LCM

42
2nd SoC development exampleThe Selective
Read-out Processor (for CMS)

• Part of the CMS electromagnetic calorimeter
  read-out
• ? Assists in on-line ECAL raw data reduction

Trigger electronics
ECAL Front-end electronics
L1 Accept
Raw data1.5 Mbyte
100 kHz
Read-out
Selective Read-outProcessor
5 µs timing budget
Selected data100 Kbyte
HLT DAQ

• Asynchronous hard real time system

43
3rd example On-board GRB Trigger and Alert
System of the ECLAIRs microsatellite

• Gamma Ray Burst study (4 to 50 keV)
• Compute in near real-time the position of the GRB
  in the sky with an accuracy of up to 10 arcmin
• Transmit this information on-ground in real-time
  and distribute it as fast as possible to other
  observatories
• On-board 2-level trigger system? first level
  counting histogram (hardware)? second level
  image processing to localize sources (software,
  FFT)
• SoC approach for Hardware/Software design of the
  DAQ/Trigger sub-system
• FPGA soft-core processor (MMU FPU) Real
  time OS?Microblaze (Xilinx, 32 bits RISC)?LEON
  (Open Source, Spark v8, ESA project)

44
Time Calibration in Neutrino Telescopes

• Two different problems
• Compare the time measured in the apparatus with
  UTC time (absolute timing calibration)
• Determine the offsets in local time measurements
  (relative timing calibration), i.e. the
  propagation time of the time-reference signal
  from onshore to offshore

Same problem for all neutrino telescopes
Same problem for all neutrino telescopes in which
data are time-stamped offshore
45
Time Calibration system
II. Optical calibration
A light pulse starts from the FCM at time known
and the arrival time is extracted from the data
flow
I. Echo calibration
The time delay for the commands to reach the
different FCMs is extracted from a go-and-return
time measurement
46
Optical timing calibration
To upper floor
An optical pulser illuminates the sensors of more
than one floor by guided light (optical fiber)
This solution allows to perform an alloptical
time calibration as well as redundancy to the
echo measuraments
From lower floor
47
Optical pulser
Among several configurations of the pulser that
we have studied, simulated and implemented, we
have finally selected one, very simple yet very
performing circuit
Analog circuit
Interface LED/fiber
Supply and voltage conditioning
remote digital control to manage the pulse
intensity in coarse and fine sensitivity
48
Tests (2)
Tests with pulser collimator splitter
1x4 fiber 40m 2 Modules PMT Hamamatsu H6780
Fall time 2.5 ns
FWHM lt 7 ns
Standard deviation of time delay from trigger lt
250 ps
49
ANTARES Numerical Clock System Features
- Provides a high stability numerical clock
signal and synchronization commands (Coded
Frames 32 bit)
- Synchronizes the control of the experiment.
RTS(Reset Time Stamp)- Start run LED
calibration - acoustic positioning system
Seismograph.
- Provides with a precision better than 500ps the
electronic relative timing of each floor and the
absolute time reference for the experiment.
- Provides a precise time calibration tool to
check the Roundtrip delays between each
electronic modules and the shore station.
50
ANTARES - Clock system Overview
300 Local Control Modules LCM clock boards
Junction Box (2) 1 to 16 passive splitters
On-shore Station
1550 nm?1310 nm
1549 nm?1532 nm
Main Electro-Optical Cable 42 km (Channels A and
B) from shore to Junction Box Single
bidirectional fibres (1549 nm / 1532 nm)
String Control Module O/E and E/O converters by
sectors (5 storeys) WDM REPs boards
Inter Link Cables 200-500 m fibre
51
ANTARES Clock test results in Lab
One?shot difference lt?gt 100 ps
Average of 100 measurements s10 ps
52
MILOM -Transit Time to SCM (MEOC delay)
6 months
53
MILOM - Delta t between Modules(relative to SCM)
LCM_TOP
MLCM
LCM_BOT
165m
115m
100m
SCM (Reference)
54
Requirement for an underwater neutrino telescope

• Monitoring of ambient parameters
• Water temperature
• Salinity
• Marine currents
• Optical properties of water (transparency)
• Periodical monitoring of system parameters
• Apparatus temperature
• Apparatus humidity
• Power dissipation of ambient instruments
• Pitch and orientation of optical modules
  mechanical framework
• Acoustic positioning system
• Instruments Control
• Power switch
• Galvanic isolation of external connections

55
SCI Board Top Layout Connection
RS232 Serial Com (galvanic isolation control)
Switched power
Instrumentation Power Supply 12V Unreg
Hardware ID selection
Microcontrollers PIC 18LF6520
Auxiliary Sensor 1 (Analog GPIO lines)
Acoustic Positioning System (RS232)
RS232 Serial Com (galvanic isolation control)
Switched power
Auxiliary Sensor 2
56
Minitower arrangement in NEMO phase 1


Acoustic Doppler Current Profiler (ADCP)

Floor 4
Compass, tilt meter,temperature sensor, humidity
sensor in each floor (Inside the Floor Control
Module)
Floor 3

Transmissometer (C-Star),
Floor 2



Conducibility Temperature Deep (CTD)
Floor 1


2 hydrophones per floor 1 hydrophone (base
tower) 1Beacon (base tower)
Base Tower
57
The architecture
58
The Data Base
59
The architecture components
On Shore Station Network
LNS Network
60
Data communication
61
Summary of this report General presentation of a
project model. A production under control Why
mass production? VLVnT2 Coordination group what
about production part ? 3 examples in case of
mass production aspect. Conclusion
VLVnT2 Catania 11/2005
LOUIS F. CEA / DAPNIA / SEDI
62
Project model From the feasibility to the
exploitation
Feasibility
Inputs outputs specifications Functions to
realize Environment Budget Time allocation Risk
analysis
Schedule
Exploitation
Specifications
Specifications
Project integration
Sub project validation
Sub project validation
Project validation
Conception Validation
Production
VLVnT2 Catania 11/2005
LOUIS F. CEA / DAPNIA / SEDI
63
The most important parts which condition the
project are the specifications of the design
based on the inputs/outputs parameters. Theses
specifications have implications not only on the
conception of the objects but also on the
production of these objects. Because all design
derived from the inputs/outputs specifications,
this information must be locked as soon as
possible and not subject to major
changes. These inputs/outputs specifications
must describe all functionalities. Because a
global validation test bench cant be available,
all steps before must guarantee that the
complete project will be operational. Both
benches and design of the objects must be
considered simultaneously. This is true for the
qualification of the object as well as for the
bench production (test burn-in for instance)
A management design group is essential in the
development of the electronic sub-projects. It
must guarantee 1/ a complete coordination
between the sub-projects. 2/ a good connection
between the design proposal and the industrial
manufacturing 3/ ensure that the final product
will meet all demands 4/ guarantee homogeneity
between all objects
VLVnT2 Catania 11/2005
LOUIS F. CEA / DAPNIA / SEDI
64
Particular Procedure
Particular Procedure
Bidiphoton burn-in
Bidiphoton qualification
Manuf. Procedure
Following card
Components soldering
Particular Procedure
Current reading bench
VLVnT2 Catania 11/2005
LOUIS F. CEA / DAPNIA / SEDI
65
Coordination design group Main type of management
Risk analysis
Technical coordination
Design
Risk analysis
Test benches
Production
Quality
Quality assurance
Production management
VLVnT2 Catania 11/2005
LOUIS F. CEA / DAPNIA / SEDI
66
Coordination design group Notion of indicator

• The notion of indicator is very important for
  production steps
• In a global production, it is NOT possible to
  check all parameters at each step
• of the life of an object.
• A few parameters must be defined within following
  domains
• system analysis processes
• risk analysis processes
• These parameters must be measurable with as
  little errors as possible and must be defined
• (High and low value for example).

Operator
Situation
Measure
Procedure
Tools
VLVnT2 Catania 11/2005
LOUIS F. CEA / DAPNIA / SEDI