EECE 631 Microcomputer System Design Lecture 9

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EECE 631Microcomputer System DesignLecture 9

• Spring 2007
• Chris Lewis
• clewis_at_ksu.edu

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Debouncing
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Project Proposals Due Next Tuesday

• Teams of 2
• 1-3 Pages typed
• Project Description
• Hardware description
• What external hardware
• Electronic
• Mechanical
• What peripherals will be used
• Software description
• Division of Labor
• Goal level of completion
• Minimal acceptable level of completion

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ABET Requirements

• List of Design Specifications
• You will be graded on how well your system meets
  these specs.
• Realistic Constraints
• These are usually overall costs, power
  consumption goals etc
• Major Technical Hurdles
• Skills necessary to meet these Hurdles
• ANY Ethical, environmental or economic concerns
• Social or societal impact of project
• ICBM
• Anti-lock brakes and airbags
• Include paragraph in final report 10pts

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Interrupts
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AIC

• 8 levels of priority
• Individually Maskable
• Vectored
• Up to 32 sources
• Level sensitive or edge triggered
• Fast forcing feature

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Detailed Block Diagram

• External Pins must be assigned via the PIO
  controller
• Power management Controller plays some role

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Vectoring
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Sources

• Peripherals
• Peripheral ID corresponds to source number/bit
  number
• External sources are termed peripherals too
• Names of Sources
• FIQ (fast source)
• SYS (source 1)
• PID2-PID31

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Mode set via AIC_SMR

• Level Sensitive
• High
• low
• Edge Triggered
• Positive
• Negative

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Operation

• Enable/Disable
• AIC_IECR
• AIC_IDCR
• Set/Clear
• AIC_ISCR
• AIC_ICCR
• Allow software interrupts
• Reading AIC_IVR automatically clears
• Not for Fast forcing interrupt
• Status
• AIC_IPR (pending)
• AIC_IMR(mask)
• AIC_ISR(status)
• AIC_CISR (current signal)

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Block Diagram
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Priority Controller

• Level 0-7 set in AIC_SMR (mode reg)
• As soon as detected nIRQ set
• If Another detected, nIRQ remains set, but read
  of AIC_IVR changes to highest priority of those
  pending
• If Another detected of same priority, lowest
  numbered source is in AIC_IVR
• nIRQ remains clear until
• Higher priority interrupt occurs (ISR must
  enable)
• AIC_EOICR (End of Interrupt Cmd Reg) is written

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Nesting

• Low priority ISR re-enables interrupts
• Higher priority ISR reads AIC_IVR
• Hardware pushes Lower priority number and
  priority level to hardware stack
• Upon AIC_EOICR write, hardware stack restores
  these values
• Hardware has 8 levels of capability

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• Key points
• Processor jumps to 0x18
• AIC_IVR contains location of ISRn
• If 0x18 contains LDR PC,PC, -F20
• Jump to ISRn
• Sets current interrupt to be pending
• De-asserts nIRQ line
• Automatically clears edge triggered
• Pushes level and number on hw stack

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FIRQ vectoring

• Processor jumps to 0x1C
• AIC_FVR contains address of FIRQ ISR
• If 0x1C has LDR PC, PC, -F20
• Jump to FISR
• Sets current interrupt to be pending
• De-asserts nIRQ line
• Automatically clears edge triggered
• Pushes level and number on hw stack

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Hardware operations

• CPSR is stored in SPSR_irq
• PC is stored in R14_irq
• PC is loaded with
• 0x18 (nIRQ)
• 0x2C (FIRQ)
• Arm core enters interrupt mode

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FIRQ mode

• R8-R13 are banked, and dont have to be saved.

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AIC_SMRn
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AIC_SVRn
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AIC_IVR
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AIC_FVR
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AIC_EOICR
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• //-----------------------------------------------
  -----------------------------
• // \fn AT91F_AIC_ConfigureIt
• // \brief Interrupt Handler Initialization
• //-----------------------------------------------
  -----------------------------
• __inline unsigned int AT91F_AIC_ConfigureIt (
• AT91PS_AIC pAic, // \arg pointer to the AIC
  registers
• unsigned int irq_id, // \arg interrupt
  number to initialize
• unsigned int priority, // \arg priority to
  give to the interrupt
• unsigned int src_type, // \arg activation and
  sense of activation
• void (newHandler) () ) // \arg address of the
  interrupt handler
• unsigned int oldHandler
• unsigned int mask
• oldHandler pAic-gtAIC_SVRirq_id
• mask 0x1 ltlt irq_id
• // Disable the interrupt on the interrupt
  controller
• pAic-gtAIC_IDCR mask