Reducing Occurrences of Priority Inversion in MSoC's using Dynamic Processor Priority Assignment

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Reducing Occurrences of Priority Inversion in
MSoC's using Dynamic Processor Priority Assignment
Mikael Collin
Research Engineer, Computer Architecture Lab (CAL)
Mladen Nikitovic
Research Engineer, Computer Architecture Lab (CAL)
Christer Norström
Senior Lecturer, Real-Time Systems Design Lab
(SDL)
Department of Computer Engineering Mälardalen
University, Västerås, Sweden
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Background
Arbitration unit
Motivation

• Interprocessor blocking and priority inversion
  on a shared bus in multiprocessor systems -
  static processor priorities - poorly assigned
  dynamic priorities

CPU 1 priority high
Task priority low
Previous efforts
CPU 0 priority low

• Static - task allocation algorithms -
  arbitration based on application profiling
• Dynamic - software for run-time programming
  of arbiter

Shared resource
Task priority high
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Proposed Solution
Arbitration unit
Dynamic arbitration

• Solution based on a Multiprocessor
  System-on-a-Chip (MSoC) with a centralised
  scheduling unit in hardware (RTU)
• Processor priority information is shared by
  adding a priority bus between the RTU and the
  arbiter using System-On-a-Chip freedom
• Processor priorities recalculated whenever
  priority changes occur in the set of currently
  executing tasks

CPU 1 priority low
Task priority low
CPU 0 priority low
Shared resource
Task priority low
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Proposed Solution
Arbitration unit
Dynamic arbitration

• Solution based on a Multiprocessor
  System-on-a-Chip (MSoC) with a centralised
  scheduling unit in hardware (RTU)
• Processor priority information is shared by
  adding a priority bus between the RTU and the
  arbiter using System-On-a-Chip freedom
• Processor priorities recalculated whenever
  priority changes occur in the set of currently
  executing tasks

CPU 1 priority low

Task priority low
CPU 0 priority high
Shared resource
Task priority high
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Benefits and Future Work
Benefits from the proposed solution

• Reduction of priority inversion scenarios
• Does not add bus traffic due to separate bus
• Decrease in interprocessor blocking for high
  priority tasks
• Better utilisation of task migration

Future Work

• Formalisation of proposed solution
• Implement simulator for system modelling and
  evaluation