DPU Subsystem Presentation

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DPU Subsystem Presentation

• Renato Orfei
• CNR-IFSI

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General Block Diagram
PACS S/S SWL DET. GRATING ASS. CHOPPER ASS.
FLIP MIRROR ASS. LWL DET.
MEC 1 MECH-CONTROL1 SWL DETECTOR CONTROL
DPU-OM
SPU-NOM
S/C
DPU-RED
SPU-RED
MEC 2 MECH-CONTRO 2 LWL DETECTOR CONTROL
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DPU General Block Diagram
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DPU High level block diagram
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CPU Block Diagram
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DC/DC Converter Block Diagram
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DPU Mass breakdown

• Components of the mass breakdownBOX
  (240x258x194 mm3, thickness 3 mm, 2.7
  g/cm3) Baseplate 240x258x3 gt 501.5 g
  Front wall 240x194x3gt 377.1 g Front wall
  connectors (deltaE)gt 150 g Bak wall
  240x194x3gt 377.1 g Lateral walls
  258x194x3x2gt 754.3 g Cover
  240x258x3gt 501.5 g Total Box weight
  2661.5 g
• CPU boards 2x 600 g gt 1200 g
• P/L I/F Boards 2x 480 g gt 960 g
• DC/DC boards 1000 g gt 1000
  g
• Motherboard 400 g gt 400 g
• Screws etc. 100 g gt
  100 g
• Cabling 300 g gt 300
  g Total estimated weight 6621.5 g (
  - 10 )

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CDMS COMMUNICATION I/F
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POWER SUPPLY I/F
28 V lines S/C operated plus synchronization from
S/C to PACS

• One I/F for DPU DC/DC converter

• Other I/Fs for SPU and DEC/MEC controlled by DPU
  via Event Pkt

S/C
DPU
SPU DEC/MEC
DC/DC
DC/DC
28Vswitches
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Subsystems Interfaces
All HW interfaces implemented with balanced
drivers and receivers (LVDS)

• 3 high speed serial bi-directional links for
  science data and HK collection - 2 links
  to/from SPU-1 link to/from DEC/MEC
• The links will be used for subsystems commanding
  and reception of science and HK data

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S/C Interface Block diagram
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