ECE994 Final Design Review Summary

1
Roadmap Towards Microelectronics for the Global
World

• ECE-994 Final Design Review Summary
• TPK
• Pizza
• ECE-715 Final Design Review Introduction
• TPK

GNAT
2
Long-term Objectives
ECE-994

• Flexible PSOC Network Architecture
• Support Homeland Security and other applications
• Tools
• Enable applications developers to develop
• Curriculum
• Prepare Undergraduate, Graduate, Practicing
  Engineers

Math Works
GNAT
3
Flexible PSOC Network Architecture Status

• 6 XUP Development Boards operational
• BIST
• Internet Access
• Analog I/O supplemental module acquired
• MicroStrain Glink
• Preliminary experience with ADXL-330
  microaccelerometer
• Applications
• Tabletop demo
• Container Security
• PLUTO

4
Tools Status

• Xilinx
• ISE
• Blockset
• Matlab/Simulink
• GNU
• PPC 405

5
Curriculum Status

• History
• ECE-994
• XUP Hardware
• Development Tools
• Class Lectures
• Current
• ECE-715
• Generic Sensor Signal Preprocessor Design Phase
• Fabrication
• Future
• ECE-715
• Test and Evaluation
• ECE-992 / IEEE Workshop
• ECE-668

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Applications

• Table-top-demo
• Find a coffee cup on the lecture table
• 4 Nodes
• Container Security
• Monitor and track cargo containers
• Detect WMD
• PLUTO
• Mines and Tunnels
• Sensor Nets and Robotics

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Table-top Demo
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Cargo Security
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ApplicationsU.S. Virtual Sea Border Project -
phase III
V. Applications Current Ambient Designs
WAN
Alarm Availability
   NI2 Center for Infrastructure Expertise
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PLUTO
V. Applications New directions Projects PLUTO

• Platform
• Internet accessible
• Laboratory
• Virtual
• Underground
• Experimental Mine Barbara
• Tunnel
• And mine related
• Observations
• Experiments
• Modeling
• Sensor evaluation and testing

14
Schematic Diagram of Experimental Gallery
V. Applications New directions Projects PLUTO

• Dense array of wireless sensor units for
• Pressure
• Temperature
• Optical Radiation
• Combined with some sensors to determine chemical
  composition

Wireless Access Point connected to Optical
Backbone
Mobile robotic sensor vehicle
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HW Technology
GNAT Node
GNAT Node
GNAT Node
GNAT Node
XUP
Virtex
GNAT Node
PPC405
Sensor
Interface
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SW Technology

• PPC
• Linux OS
• C-Code
• Network
• MPI
• OS

17
ECE994 Goal

• Develop Curriculum and materials to prepare
  students to design and implement microelectronic
  systems using best practices of the US high
  tech industry today
• Integration of IP modules and sensor devices with
  FPGA-based SoC
• Networking of SoCs
• Global Network Academic Test --
• Collaborative and distant learning techniques for
  distributed team management and design
• In-situ and remote development scenarios

18
ECE994 Additional Support

• MicroStrain, Inc.
• www.microstrain.com
• IRobot, Corp.
• www.irobot.com
• Analog Devices
• www.analog.com
• Intellitech
• www.intellitech.com

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ECE994 FDR
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Sit! Rest!
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Roadmap Towards Microelectronics for the Global
World
Manga...Manga...Eat...Eat!!!
Ready to Resume
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Resume
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Roadmap Towards Microelectronics for the Global
World

• Introduction
• Prof Andrzej Rucinski
• GNAT
• ECE-994 Final Design Review
• Class
• Pizza
• IEEE
• ECE-715 Final Design Review
• Class

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ECE715 FDR
25
ADXL330 Basic unit cell sensor building block
26
EVAL-ADXL330Z
27
Overall Generic Sensor Network
28
Node Top-Level Diagram
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Generic Preprocessor Top-level Diagram
30
Thank You

• Muchas Gracias
• Dziekuje za uwage

31
Thanks
32
END Presentation

• Following slides for backup only
• DO NOT PRINT

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ECE994 Programmable System on a Chip (PSoC) Design
The UNH and the University of Tennessee are
offering this course in PSoC systems engineering
in response to the challenges of

• flat world, globalization and outsourcing
  facing todays engineering profession
• and the demand for systems engineers by major
  United States employers

TECHNICAL CURRENCY PROGRAMS
34
XUPV2P Block Diagram
35
XUPV2P BIST
36
G-Link COTS Wireless Sensor Node
37
Microstrain G-Link
V. Current technology trends and COTS COTS
Wireless Sensing
58 mm

• Supports simultaneous streaming from multiple
  nodes to PC
• Available with 2g or 10g range
• Datalogging rates up to 2048 Hz
• Real-time streaming rates up to 736 Hz
• On-board memory stores up to 1,000,000
  measurements
• Communication range up to 70m line-of-sight
• Low power consumption for extended use

38
Conceptual Block Diagram
V. Applications Current Ambient Designs
presented at SiCon 02 S.W. Arms, T.P. Kochanski,
et. al.
39
V. Applications New directions Projects PLUTO
Experimental Mine Barbara
Virtual Mine Barbara
Gdansk
40
ADXL330 Basic unit cell sensor building block
41
EVAL-ADXL330Z
42
The University of New Hampshire and the National
Infrastructure Institute thanks you for attending
today!
43
ADXL330 FEATURES

• 3-axis sensing /- 3g Full Scale
• Small, low-profile package
• 4 mm 4 mm 1.45 mm LFCSP
• Low power
• 180 µA at VS 1.8 V (typical)
• Single-supply operation
• 1.8 V to 3.6 V
• 10,000 g shock survival
• Excellent temperature stability
• BW adjustment with a single capacitor per axis
• RoHS/WEEE lead-free compliant

44
ADXL330 Operation

• The surface micromachined sensor element is made
  by
• depositing polysilicon on a sacrificial oxide
  layer
• then etched away leaving the suspended sensor
  element
• The actual sensor has tens of unit cells
• Uses differential capacitor (CS1 and CS2) formed
  by
• center plate -- part of the moving beam
• and two fixed outer plates
• The two capacitors
• equal at rest (no applied acceleration)
• When acceleration is applied, the mass of the
  beam causes it to move closer to one of the fixed
  plates while moving further from the other
• This change in differential capacitance is then
  interrogated

45
Conditioning Electronics
46
Conditioning Electronics

• 1MHz square wave drives the fixed capacitor
  plates
• differentially by a the two square wave
  amplitudes 180º out of phase
• When at rest
• the two capacitors C1 C2
• voltage output at their electrical center 0
• When the beam begins to move
• Delta capacitance produces an output signal at
  the center plate
• Output amplitude increase with the acceleration
• Output from center plate is buffered by A1 and
  applied to a synchronous demodulator
• The direction of beam motion affects the phase of
  the signal
• synchronous demodulation extracts the amplitude
  information
• output is amplified by A2 to produce VOUT the
  acceleration output voltage

47
ADXL330
48
Nonlinear error in accelerometer sensor response
over the 5gacceleration range.
49
Magnitude of gravitational acceleration as the
sensor is rotated in a circle
50
A/D Error Sources

• Quantization error
• Non-linearity
• Aperture error

51
Sensor Processing Block Diagram
Sampling Clock
A/D Quantization
Analog Signal Conditioning
Anti-aliasing Filter
Sensing Transducer
Sampling
Digitized Signal
52
Nyquist
53
Anti-Aliasing
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Signal to Noise

• Noise gt 0 ! For all T gt 0
• PNoise B
• Signal to Noise PSignal / PSignalNoise
• Dynamic Range
• Full Scale Range
• Headroom
• Floating Point

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Sensor Processing Block Diagram
Sampling Clock
A/D Quantization
Analog Signal Conditioning
Anti-aliasing Filter
Sensing Transducer
Sampling
Digitized Signal
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What is a Sensor Network
Signal Conditioning
Sensor
Control
Processing
Comm
Storage
Comm Link
User Interface
User
Model
57
Node Architecture - SoC
Current technology trends and COTS Current
Ambient Designs

• Technology
• FPGA Xillinx, Altera, Actel
• Functions
• (Capabilities / IP Cores)
• Wireless communication
• Cryptography
• Management
• Internet Protocol Signalization
• I/O bus - sensors

Wireless Antenna 1
Wireless Antenna 2
Switch
Communication
FPGA SoC
Management
Cryptography
CPU
I/O bus
Digital Lock
External sensors
GPS
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Microstrain G-Link
V. Current technology trends and COTS COTS
Wireless Sensing
58 mm

• Supports simultaneous streaming from multiple
  nodes to PC
• Available with 2g or 10g range
• Datalogging rates up to 2048 Hz
• Real-time streaming rates up to 736 Hz
• On-board memory stores up to 1,000,000
  measurements
• Communication range up to 70m line-of-sight
• Low power consumption for extended use

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iSensorTM
60
ADXL330 Package
61
BANDWIDTH Limiting withCX, CY, AND CZ

• Capacitors added to XOUT, YOUT, and ZOUT pins to
  implement low-pass filtering for
• antialiasing
• and noise reduction
• The equation for the 3 dB bandwidth is
• F-3 dB 1/(2p(32 kO) C(X, Y, Z))
• or more simply F3 dB 5 µF/C(X, Y, Z)
• The tolerance of the internal resistor (RFILT)
  typically varies as much as 15 of its nominal
  value (32 kO)
• the bandwidth varies accordingly
• A minimum capacitance of 0.0047 µF for CX, CY,
  and CZ is recommended in all cases

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Capacitance vs Bandwidth
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ADXL330 Noise

• Has the characteristics of white Gaussian noise
• contributes equally at all frequencies and is
  described in terms of µg/vHz
• (the noise is proportional to the square root of
  the accelerometer bandwidth)
• The user should limit bandwidth to the lowest
  frequency needed by the application to maximize
  the resolution and dynamic range of the
  accelerometer

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Typical noise of the ADXL330

• With the single-pole, roll-off characteristic
  determined by

65
Peak-to-Peak Noise

• Peak value of the noise can only be estimated by
  statistical methods
• Table of probabilities of exceeding various peak
  values, given the rms value

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Estimate of Peak-to-Peak Noise
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Noise Signal
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SELF TEST with ST Pin

• When ST pin is set to VS, an electrostatic force
  is exerted on the accelerometer beam
• The resulting movement of the beam allows the
  user to test if the accelerometer is functional
• The typical change in output is -500 mg
  (corresponding to -150 mV) in the X-axis, 500 mg
  (or 150 mV) on the Y-axis, and -200 mg (or -60
  mV) on the Z-axis
• ST pin may be left open circuit or connected to
  common
• (Never expose the ST pin to voltages greater than
  VS 0.3 V.
• If this cannot be guaranteed due to the system
  design (for instance, if there are multiple
  supply voltages), then a low VF clamping diode
  between ST and VS is recommended

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ADXL330

• A complete 3-axis acceleration measurement system
  on a single monolithic IC
• Measurement range of 3 g minimum
• Contains a polysilicon surface micromachined
  sensor and signal conditioning circuitry to
  implement an open-loop acceleration measurement
  architecture
• The output signals are analog voltages that are
  proportional to acceleration

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ADXL330

• Polysilicon surface micromachined structure built
  on top of a silicon wafer
• Polysilicon springs suspend the structure over
  the surface of the wafer and provide a resistance
  against acceleration forces
• Deflection is measured using a differential
  capacitor that consists of independent fixed
  plates and plates attached to the moving mass
• The fixed plates are driven by 180 out-of-phase
  square waves
• Acceleration deflects the moving mass and
  unbalances the differential capacitor
  proportional to acceleration
• Phase-sensitive demodulation gives acceleration
  magnitude and direction
• The user then sets the signal band-width of the
  device by adding a capacitor to ground
• The demodulator output is amplified and brought
  off-chip through a 32 kO resistor
• This filtering improves measurement resolution
  and helps prevent aliasing

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Xilinx Virtex II Development Board for XUP
72
MicroBlaze-based Embedded Design
I-Cache BRAM
Local Memory Bus
Flexible Soft IP
BRAM
Configurable Sizes
D-Cache BRAM
Off-Chip Memory
FLASH/SRAM
73
PowerPC-based Embedded Design
Full system customization to meet performance,
functionality, and cost goals
74
Clive Max MaxfieldThe Design Warriors Guide
to FPGAs Devices Tools, and FlowsElsevier 2004
Price 67.93Format  Adobe Reader PDF
www.ebookmall.com/ebook/149053-ebook.htm
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Traditional VLSI Design Flow
79
Why PSOC

• Obvious advantage simpler and quicker design
  . most of the design is already done
• Cell arrays, mask programmable gate arrays
• Field Programmable devices PLD, FPGA
• Less obvious easier re-use, modularity
• Still less obvious easier collaborative and
  remote design
• May be cheaper
• More flexible
• Easy to fix
• Reconfigurable on the fly

80
Why Not PSOC until recently

• Not enough capabilities
• Clock speed
• Gates
• I/O
• Memory
• Less developed tools
• Too Expensive
• Too hard to test and verify
• Now on-chip monitoring

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Cost of Masks
82
Cost of Fabs
83
Trade-offs

• Mask sets now define costs of full custom
• Need very large volume and no changes to justify
• Design personnel and tools as well as time to
  market now define the bounds of ASICs
• Cost of raw devices now define the bounds of FPGA
  and PSOC

84
Systems Implementation
85
Intelligent Sensor Network Functions
II. Key pieces of the core technology

• Determine the local value of some parameter
• Multiple types of sensors with different sampling
  rates
• Detect events of interest and estimate
  parameters  
• traffic entering intersection / speed
• Classify a detected object  
• Is a vehicle a car, a mini-van, a light truck, a
  bus, etc.
• Track an object
• Follow an emergency vehicle en route to a fire

86
Network Self-organization Essential
II. Key pieces of the core technology

• Given
• The large number of nodes
• Potential hostile locations
• Nodes failure
• Individual nodes may become disconnected
• New nodes may join the network
• To maintain high degree of overall connectivity
  manual configuration is not feasible
• Must be able to periodically reconfigure itself

87
Collaborative signal processing  
II. Key pieces of the core technology

•  Improve performance in the detection/estimation
  of events of interest
• Useful to fuse data from multiple sensors
• Requires transmission of both data and control
  messages
• May put constraints on the network architecture

88
Querying Ability  
II. Key pieces of the core technology

• May want to query
• individual nodes
• group of nodes in a region
• Data fusion drives required network Bandwidth
• Network connectivity and bandwidth may limit
  amount of the data transmitted across the network
• Local sink nodes will collect the data from a
  given area and can create summary messages
• Direct query to the regional sink node
• Possible penalty is increased response time

89
Sit! Rest!
90
Part 2 Rest stop
91
Virtex-II Pro Development SystemCurriculum on a
Chip
92
Hardware Reference Manual
93
XUPV2P Features

• Virtex-2 Pro XC2VP30 FPGA with
• 30,816 Logic Cells
• 136 18-bit multipliers,
• 2,448Kb of block RAM,
• 2 PowerPC Processors
• DDR SDRAM DIMM that can accept up to 2Gbytes of
  RAM
• 10/100 Ethernet port
• USB2 port
• Compact Flash card slot
• XSGA Video port
• Audio Codec
• SATA, and PS/2, RS-232 ports
• High and Low Speed expansion connectors,
• large collection of available expansion boards

94
XUPV2P

• Can function as a
• digital design trainer,
• microprocessor development system,
• host for embedded processor cores and complex
  digital systems.
• Expansion connectors can accommodate
  special-purpose circuits and systems for years to
  come
• Supported by world-class design tools, including
• ISE Foundation,
• Chipscope-Pro,
• Embedded Developer's Kit (EDK),
• and System Generator (WebPack cannot be used).
• Applications that include an embedded processor
  require EDK, and those that do not include a
  processor can use ISE

95
XUPV2P Block Diagram
96
XUPV2P BIST
97
Demonstration Reference Designs 

• XUPV2P Demonstration Design uses the AC 97 audio
  codec as the audio A/D and D/A to the Xilinx
  XC2VP30 FPGA, for capturing audio to be filtered
  and played back to the user's speakers.
• Video Decoder using VDEC-1 uses an Analog Devices
  ADV7183B to sample the incoming analog video and
  convert it to digital values according to the
  video standards ITU-R.656 and ITU-R BT.601.
• Slide Show using 256 MB DDR Memory reads binary
  graphic data (.bmp) stored on a compact flash and
  presents it on an external display monitor.
• Ethernet MAC OneWire implements a web server
  running on the XUP-V2Pro Development System, with
  a OneWire core. The WEB server will display the
  user DIP switches and control the LEDs from your
  browser.
• OneWire implements a a OneWire core. The core
  reads the silicon serial number and displays it
  on the terminal window through a UART.  
• PS2 implements a core which reads in the
  characters typed in on a keyboard connected to
  either of the two PS2 ports and displays it on
  the terminal window through a UART.
• Edge Detection shows how a 2-D Image filter can
  be efficiently realized using n-tap MAC FIR
  Filters.

98
XUPV2P Demonstration Design

• Uses the AC 97 audio codec as the audio A/D and
  D/A to the Xilinx XC2VP30 FPGA, for capturing
  audio to be filtered and played back to the
  user's speakers.
• The filtered or unfiltered digital audio data is
  presented to a 64 point FFT to convert the time
  domain audio, to frequency domain spectral
  information.
• The output of the FFT is sampled and displayed
  graphically using character mapped graphics to an
  800 X 600 pixel VGA resolution display using
  Fairchild FMS3818 D/A to take the digital data
  from the FPGA to the SVGA analog output. 

99
Power PC 405 Block
100
Valuable Reference Docs
101
Virtex-II Platform FPGA User Guide

• Chapter 1, The Virtex-II Pro / Virtex-II Pro X
  FPGAFamily
• Chapter 2, Timing Models
• Chapter 3, Design Considerations
• Chapter 4, Configuration
• Chapter 5, PCB Design Considerations
• Appendix A, BitGen and PROMGen Switches and
  Options
• Appendix B, Platform Flash Family PROMs
• Appendix C, Choosing the Battery for VBATT

102
PowerPC Processor Reference Guide

• Introduction to the PPC405, provides a general
  understanding of the PPC405 as an implementation
  of the PowerPC embedded-environment architecture.
• Operational Concepts, introduces the processor
  operating modes, execution model,
  synchronization, operand conventions, and
  instruction conventions.
• User Programming Model, describes the registers
  and instructions available to application
  software.
• PPC405 Privileged-Mode Programming Model,
  introduces the registers and instructions
  available to system software.
• Memory-System Management, describes the operation
  of the memory system, including caches. Real-mode
  storage control is also described in this
  chapter.
• Virtual-Memory Management, describes
  virtual-to-physical address translation as
  supported by the PPC405. Virtual-mode storage
  control is also described in this chapter.

103
PowerPC Processor Reference Guide

• Exceptions and Interrupts, provides details of
  all exceptions recognized by the PPC405 and how
  software can use the interrupt mechanism to
  handle exceptions.
• Timer Resources, describes the timer registers
  and timer-interrupt controls available in the
  PPC405.
• Debugging, describes the debug resources
  available to software and hardware debuggers.
• Reset and Initialization, describes the state of
  the PPC405 following reset and the requirements
  for initializing the processor.
• Instruction Set, provides a detailed description
  of each instruction supported by the PPC405.

104
PowerPC Processor Reference Guide

• Register Summary, is a reference of all registers
  supported by the PPC405.
• Instruction Summary, lists all instructions
  sorted by mnemonic, opcode, function, and form.
  Each entry for an instruction shows its complete
  encoding. General instruction-set information is
  also provided.
• Simplified Mnemonics, lists the simplified
  mnemonics recognized by many PowerPC assemblers.
  These mnemonics provide a shorthand means of
  specifying frequently-used instruction encodings
  and can greatly improve assembler code
  readability.
• Programming Considerations, provides information
  on improving performance of software written for
  the PPC405.
• PowerPC 6xx/7xx Compatibility, describes the
  programming model differences between the PPC405
  and PowerPC 6xx and 7xx series processors.
• PowerPC Book-E Compatibility, describes the
  programming model differences between the PPC405
  and PowerPC Book-E processors.

105
PowerPC 405 Processor Block Reference
GuideEmbedded Development Kit

• Chapter 1, Introduction to the PowerPC 405
  Processor, provides an overview of the PowerPC
  embedded-environment architecture and the
  features supported by the PowerPC 405 processor
  block.
• Chapter 2, Input/Output Interfaces, describes
  the interface signals into and out of the PowerPC
  405 processor block. Where appropriate, timing
  diagrams are provided to assist in understanding
  the functional relationship between multiple
  signals.
• Chapter 3, PowerPC 405 OCM Controller,
  describes the features, interface signals, timing
  specifications, and programming model for the
  PowerPC 405 on-chip memory (OCM) controller. The
  OCM controller serves as a dedicated interface
  between the block RAMs in the FPGA and OCM
  signals available on the embedded PowerPC 405
  core.
• Chapter 4, PowerPC 405 APU Controller,
  describes the Auxiliary Processor Unit
  controller, which allows the designer to extend
  the native PowerPC 405 instruction set with
  custom instructions that are executed by an FPGA
  Fabric Co-processor Module (FCM). The APU
  controller is available only for Virtex-4 family
  devices.

106
PowerPC 405 Processor Block Reference
GuideEmbedded Development Kit

• Appendix A, RISCWatch and RISCTrace Interfaces,
  describes the interface requirements between the
  PowerPC 405 processor block and the RISCWatch and
  RISCTrace tools.
• Appendix B, Signal Summary, lists all PowerPC
  405 interface signals in alphabetical order.
• Appendix C, Processor Block Timing Model,
  explains all of the timing parameters associated
  with the IBM PPC405 Processor Block.

107
Current Technology Trends and COTS
IV. Current technology trends and COTS

• Network Architectures
• Processor Scalability
• COTS Wireless Sensor Elements

108
NIST on Sensor Network Architecture
IV. Current technology trends and COTS
Network Architecture for Ambient Intelligence

• With the coming availability of low cost, short
  range radios along with advances in wireless
  networking, it is expected that wireless ad hoc
  sensor networks will become commonly
  deployed...Each node may have sufficient
  processing power to make a decision, and it will
  be able to broadcast this decision to the other
  nodes in the cluster.  One node may act as the
  cluster master, and it may also contain a longer
  range radio using a protocol such as IEEE 802.11
  or Bluetooth -- http//w3.antd.nist.gov/wahn_ssn.s
  html

109
Processor Performance
IV. Current technology trends and COTS Processor
Scalability
110
G-Link COTS Wireless Sensor Node
111
Microstrain G-Link
V. Current technology trends and COTS COTS
Wireless Sensing
58 mm

• Supports simultaneous streaming from multiple
  nodes to PC
• Available with 2g or 10g range
• Datalogging rates up to 2048 Hz
• Real-time streaming rates up to 736 Hz
• On-board memory stores up to 1,000,000
  measurements
• Communication range up to 70m line-of-sight
• Low power consumption for extended use

112
Net - Internet
113
Discussion of ECE-994 Project

• Major portion of the ECE-994
• Should relate to the technical material in the
  course i.e. PSOC or FPGA
• Should be based and take full advantage of the
  XUP Development Kit
• Should be related to the work of the Rucinski
  Group and the CIDL
• Is most successful when it involves all
  collaboratively

114
ECE-994 Project

• A major focus of CIDL and Rucinski Group is on
  Distributed Sensor Networks that feature
• Ad-hoc robust and efficient network capability
• coming and going of nodes without a reboot
• Self organization or self reorganization to
  optimize performance
• Distributed processing and storage
• Capability of interfacing with many types of
  sensors
• Based on standards and opensource as much as
  possible
• Maximal adaptability, reconfigurability to serve
  many possible applications in security and safety

115
ECE-994 Project Ideas

• Building a concept demo of a generic node in a
  sensor network
• Combine core FPGA for control and processing with
  external
• sensors
• A/D such as the Digilent AIO1
• http//www.digilentinc.com/Products/Detail.cfm?Pro
  dAIO1Nav1ProductsNav2Accessory
• Communications
• Based on MPI for network OS and coordination

116
ECE-994 ProjectTasks

• Form the team chose a team leader
• Research the XUP Development Kit
• Decide on a preferred project and a back-up
• Decide on who is responsible for what aspect and
  the timetable
• Develop your formal Project Proposal and
• be prepared to formally present it

117
Ambient Node in an Intelligent Network
Applications
V. Applications Current Ambient Designs

• Web Interrogation / U.S. Virtual Sea Border -NI2
  Project
• PLUTO -- Tunnel, Mine Monitoring System Project
• Ocean Deep Underwater Research Project
• Intelligent Communication Network Project

118
Ambient Node in an Intelligent Network US Virtual
Sea Border Project
V. Applications Current Ambient Designs

• Phase I Interactive Communication Link ICL -
  (secure chat audio/video communication between
  captain deck and command control third party)
• Phase II Security Managements System - SMS - (
  phase I the management system with container
  communication, Node availability checking,
  Graphical interface for command control and
  website access for the end users (like cargo,
  ship, etc, owners))
• Phase III Ambient Security Control System -
  ASCS ( phase II more node sophisticated sensors
  with node display and portable controller
  scanners for investigation team)

   NI2 Center for Infrastructure Expertise
119
ApplicationsU.S. Virtual Sea Border Project -
phase III
V. Applications Current Ambient Designs
WAN
Alarm Availability
   NI2 Center for Infrastructure Expertise
120
Container Security System Design Criteria
V. Applications Current Ambient Designs

• Distributed processing minimizes need for on the
  air bandwidth and lowers system power
  consumption
• Each device has unique address, network is ad
  hoc
• Node based data storage for storing dynamic
  waveforms
• Capable of deployment of over 1000 nodes, using
  one RF transmission frequency to one receiver
• Small size, easy to place in the field
• Low power, long battery life
• Long transmission range
• Capable of automated Internet data delivery

121
Container Security System Architecture
V. Applications Current Ambient Designs

• Encrypted digital data is transmitted via a TDMA
  wireless network (1/3 mile range), to a local
  receiver
• An 802.11b hierarchical, spoke-and-hub receiver
  network (1-2 mile range), enables monitoring of
  thousands of individual sensors and containers
• Additional Features
• Advanced signal processing
• Geolocation
• Intelligent triggering
• Local storage
• Local interrogation with portable receivers.

122
Conceptual Block Diagram
V. Applications Current Ambient Designs
presented at SiCon 02 S.W. Arms, T.P. Kochanski,
et. al.
123
Concept of PLUTO
V. Applications New directions Projects PLUTO

• Satisfy requirement for flexible, accessible
  testbed to
• Gather experimental data for validation
• Develop and test operational sensors
• Platform Laboratory for Underground and Tunnel
  Observations
• Use an experimental underground mine as a
  laboratory to perform experiments to model mines
  and tunnels
• Polands Central Mining Institute operates the
  Experimental Mine Barbara that provides an
  ideal testbed
• George Markowsky et. al., "Anywhere, Anytime,
  Any Size, Any Signal Scalable, Remote
  Information Sensing and Communication Systems",
  2002
• Kazimierz Lebecki, "Zagrozenia Pylowe w
  Górnictwie", 2004

124
PLUTO
V. Applications New directions Projects PLUTO

• Platform
• Internet accessible
• Laboratory
• Virtual
• Underground
• Experimental Mine Barbara
• Tunnel
• And mine related
• Observations
• Experiments
• Modeling
• Sensor evaluation and testing

125
Schematic Diagram of Experimental Gallery
V. Applications New directions Projects PLUTO

• Dense array of wireless sensor units for
• Pressure
• Temperature
• Optical Radiation
• Combined with some sensors to determine chemical
  composition

Wireless Access Point connected to Optical
Backbone
Mobile robotic sensor vehicle
126
V. Applications New directions Projects PLUTO
Experimental Mine Barbara
Virtual Mine Barbara
Gdansk
127
Node Architecture - SoC
V. Applications New directions SOC Architecture

• Technology
• FPGA Xillinx, Altera, Actel
• Functions
• (Capabilities / IP Cores)
• Wireless communication
• Cryptography
• Management
• Internet Protocol Signalization
• I/O bus - sensors

Wireless Antenna 1
Wireless Antenna 2
Switch
Communication
FPGA SoC
Management
Cryptography
CPU
I/O bus
Digital Lock
External sensors
GPS
128
Architecture Node FPGA Implementation
V. Applications New directions SOC Architecture
129
Ambient Node in an Intelligent Network
Applications Future Steps
V. Applications New directions Future Steps

• Ambient Network
• Power Management
• Signalization of Sensors Network
• Inter-network communication
• Node Addressing
• US VSB Project
• Cargo container anomalies specification
• Procedures Countermeasures

130
Sensor Networking and Synthetic RealityOutline

• I. Introduction and definitions
• II. Key pieces of the core technology
• III 1950s digital sensor networking
• IV. Current off the shelf technology
• V Applications
• VI. Areas that still need lots of work and the
  future
• VII. Conclude

131
Key Technical Challenges

• VI. Areas that still need lots of work and the
  future

• Efficient networking configuration and routing
• To enable rapid, ad hoc networking of any number
  of either fixed or mobile devices
• Collaborative signal and information processing
• To detect, classify, and track events and
  localized patterns of events
• Distributed microdatabases over a spatio-temporal
  interval
• Stored in the devices
• Queriable by multiple users
• Methods for dynamic programmability of the
  network
• Methods for security and information assurance to
  enable
• Intrusion detection, intrusion tolerance, and
  survivable operation in the face of failure and
  compromise
• Power efficient elements
• Interactive, dynamic fully-immersive, real-time
  access
• Middleware for remote, secure, control and access
• User-friendly development tools for the
  applications creators

132
What of the future?Highly speculative no
promises
VI. Areas that still need lots of work and the
future

• Sensors with great sensitivity, specificity and
  flexibility
• Nano-scale and meso-scale?
• Fully integrated plug and play sensor modules
  with signal processing, storage and
  communications in a single package
• Global, collaborative real-time access to sensor
  networks
• Sensors that know what you want to find out and
  can be your friend

133
Sensor Networking and Synthetic RealityOutline

• I. Introduction and definitions
• II. Fundamentals of sensors and signals
• III. Key pieces of the core technology
• IV. Project Lincoln
• 1950s digital sensor networking and synthetic
  reality
• V. Current off the shelf technology
• VI. New directions Projects NEPTUNE, VLAB, PLUTO
  
• VII. Areas that still need lots of work and the
  future
• VII. Conclude

134
Some Observations

• VII. Conclude

• System perspective is critical to success
• Only as good as integrated hw / sw
• Reusability modularity of hardware
• Reusability modularity of software
• Software is far behind Hardware in
  price/performance, improvement/decade\
• Lacking Easy to use Tools for Wireless
  Communications
• Design, Implementation and Testing
• Need for collaboration on all scales
• Synergistic Model MIT Model Combine
• University fundamental r and concept d,
  education and training
• with industrial applied rd
• And entrepreneurial funding sources

135
References Links
VII. Conclude

• Ambient Intelligence http//ambient.media.mit.edu
  /vision.html, http//courses.media.mit.edu/2005spr
  ing/mas961/readings.html,
• Signal Processing http//www.techonline.com/commu
  nity/ed_resource/20771, http//www.dspguide.com/pd
  fbook.htm
• NIST Sensor Networks http//w3.antd.nist.gov/wahn
  _ssn.shtml
• Blue Gene http//www.internetnews.com/ent-news/ar
  ticle.php/3432221
• Cell Processor http//cell.scei.co.jp/index_e.htm
  l, http//www.mc.com/products/view/index.cfm?id96
  typeboards
• Bluetooth http//www.bluetooth.com/bluetooth/
• NEPTUNE, etc.http//www.whoi.edu/mr/pr.do?id1578
  
• CAVE http//www.cs.vu.nl/7Erenambot/vr/cases/mol
  .htm, http//www.evl.uic.edu/pape/CAVE/
• Fledermaushttp//www.ivs3d.com/products/technolog
  y/thebat.html
• More VR http//www.sgvl.geo.su.se/index.php?optio
  ncom_contenttaskviewid42Itemid148,
  http//www.ccom-jhc.unh.edu/, http//archive.ncsa.
  uiuc.edu/Cyberia/VETopLevels/VR.Interface.html,
  http//www.ccom.unh.edu/vislab/CenterofWorkspaceIn
  teraction.mov http//www.research.ibm.com/journal
  /sj/393/part3/paradiso.html
• VLAB http//vlab.psnc.pl/gen_info.html
• MIT ILAB http//icampus.mit.edu/ilabs/
• Central Mining Institute http//www.gig.katowice.
  pl/gig/index_english.php
• Microstrain Wireless Modules http//www.microstra
  in.com/2400g-link_specs.aspx
• MIT Project Oxygen http//oxygen.lcs.mit.edu/Kno
  wledgeAccess.html
• SAGE, Project Lincoln http//www.mitre.org/about/
  photo_archives/sage_photo.html

136
CONTACT INFO

• VII. Conclude

• University of New Hampshire, Durham, NH, USA
• Thaddeus Paul Kochanski, Ph.D.
• Tel [phone]
• tpz4_at_unh.edu
• tedpk_at_alum.mit.edu
• Andrzej Rucinski, Ph.D.
• Tel [phone]
• andrzej.rucinski_at_unh.edu
• Central Mining Institute, Katowice, Poland
• Kazimierz Lebecki, D.Sc.
• Tel [phone], mobile [phone]
• kazimierz.lebecki_at_neostrada.pl
• http//www.gig.katowice.pl/gig/index_english.php

137


ECE994.
Programmable System-on-a-Chip (PSoC) Design 2007
IEEE International Conference on Microelectronic
Systems Education (http//www.mseconference.org/)
and the Special Issue of IEEE
Transactions on Education IEEE Computer
Society IEEE Critical Infrastructure
Dependability Initiative and the IEEE Central New
England Council Mentor Graphics High Education
Program (http//www.mentor.com/company/higher
ed/index.cfm) XILINX University Program
(http//www.xilinx.com/univ/index.htm)
Textbook Clive Max Maxfield, The Design
Warriors Guide to FPGAs Devices Tools, and
Flows, Elsevier 2004 First,
138

ECE994. Programmable System-on-a-Chip (PSoC)
Design Catalog Description Overview of Field
Programmable Gate Arrays (FPGAs),
Application-Specific Integrated Circuits (ASICs),
System-on-a-Chip (SoC), and Programmable SoC
(PSoC) networks and constellations. Intellectual
Property (IP) module design in VHDL and synthesis
oriented implementation using multiple
technologies (Altera and Xilinx). Integration
of IP modules and sensor devices with an existing
SoC. Collaborative and distant learning
techniques for distributed team management and
design. In-situ and remote development scenarios.
4 credits Lab. The goal of the experimental
course is to prepare students to design and
implement microelectronic systems using best
practices of the US high tech industry today.
Course Coordinator Dr. Andrzej Rucinski,
University of New Hampshire Kingsbury W321,
andrzej.rucinski_at_unh.edu, 603-862-1381 Instructor
s Dr. Don Bouldin, University of Tennessee
Programmable System-on-a-Chip (PSoC) Dr. Kent
Chamberlin, University of New Hampshire Global
Education Microelectronic Systems network
(GEMS) Dr. Ted Kochanski, University of New
Hampshire - Global Ambient Intelligence Network
(GAIN)
139
Milestones

• Ted is making an automated graph here
• ECE715 (since 1986)
• ECE777 (since 1995)
• ECE911 (Spring 2006)
• IEEE Workshop (Fall 2005)
• ECE994 (Fall 2006)
• ECE992/ECE777/IEEE Workshop (Spring 2007)

140
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