Improving Compression Ratio, Area Overhead, and Test Application Time in System-on-a-chip Test Data Compression/Decompression

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Improving Compression Ratio, Area Overhead, and
Test Application Time in System-on-a-chip
Test Data Compression/Decompression

• Paul Theo Gonciari, Bashir Al-Hashimi and
  Nicola Nicolici
• University of Southampton, UK
• McMaster University, Canada

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Why Test Data Reduction ?

• Exponential increase in volume of test data
  (ITRS)
• 60 of ATE upgrade caused by memory (EETimes)
• Solutions
• Built-in self-test (BIST)
• Test data reduction
• Useful
• Useless
• Useful
• Compaction
• does not reduce bandwidth
• Compression
• reduces bandwidth
• further reduces test time

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Overview

• Test data compression (TDC)
• Environment
• Previous work
• Variable-length Input Huffman Coding (VIHC)
• Compression algorithm
• Decompression architecture
• Experimental results
• Conclusions Future work

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Test Data Compression (TDC)

• Post ATPG process
• Reduces size of test set
• Exploits nature of test sets
• Mapping
• Reordering
• Difference sequence
• Exploits nature of patterns
• Length
• Type
• Requires on-chip decoder

ATPG
Initial test set
Test data compression
Compressed test set
Test vector database
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TDC Environment (TDCE)

• Compression ratio
• Mapping reordering
• Type of input patterns
• Length of the pattern
• Compression algorithm
• Area overhead
• Nature of decoder
• Type of input pattern
• Length of pattern
• Test application time (TAT)
• Nature of decoder
• Length of pattern
• Frequency ratio

ATE
reduced bandwidth
on-chip decoder
Initial test set
CUT
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TDC Previous Work

• Selective Coding (SC) Jas et. al VTS99
• large decoder
• parallel decoder
• low TAT
• Golomb codes Chandra et. al TCAD01
• small decoder
• serial decoder
• large TAT
• FDR codes Chandra et. al VTS01
• fixed size decoder
• serial decoder
• large TAT

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Variable-length Input Huffman Coding

• Variable-length Input Huffman Coding (VIHC)
• Employs variable-length input patterns
• Uses Huffman coding to obtain optimum code
• Uses parallel on-chip decoder to reduce TAT
• Compression Algorithm
• Step 1 - Prepare initial test set
• mapping dont cares
• reordering
• number of 1s in the difference is minimum
• minimum run of 0s maximum
• Step 2 - Huffman code computation
• exploits variable length patterns
• Step 3 - Generate decoder information
• determines the on-chip decoder

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VIHC - Code Computation
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VIHC vs. Golomb TCAD01
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VIHC Decoder

• VIHC parallel on-chip decoder
• Huffman decoder
• Control and Generation Unit (CGU)

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Compression Ratio Comparison
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Area Overhead Comparison
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Test Application Time Comparison
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Comparison Overview
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Conclusion Future Work

• Proposed
• New VIHC method
• New compression/decompression scheme
• Improves all the TDCE parameters
• Good compression ratio
• Small area overhead
• Low test application time
• Future work
• Reduce synchronization overhead
• Exploit core wrapper design for TDC