ECE-C662 Introduction to Behavioral Synthesis Knapp Text Ch. 1-2 Prawat Nagvajara

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ECE-C662 Introduction to Behavioral
SynthesisKnapp Text Ch. 1-2Prawat Nagvajara

• Design flow
• Simulation and verification
• RTL and behavioral design
• Behavioral compiler
• Design flow
• Representation
• Allocation
• Netlisting
• Control FSM
• Compiler outputs

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• Design flow

Control synthesis
Dataflow synthesis
Behavioral synthesis
RTL synthesis
Logic synthesis
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Domain-Specific Synthesis

• Dataflow oriented synthesis
• Input data are streams of samples
• Operations on data are stream oriented
• Signal flow diagrams, e.g., x axz-1 bu or
  xk axk-1 buk
• Signal processing applications, e.g., filtering,
  modulations, etc.
• Languages and schematic capture editors available
• Outputs are HDL description to behavioral or RTL
  synthesis tool

4

• Control flow oriented synthesis
• Finite state machines
• States and their transitions
• Input data are conditions
• Hierarchical descriptions
• Languages and schematic capture editors available
• Outputs are HDL description to behavioral or RTL
  synthesis tool

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Behavioral Synthesis

• Back end for control flow and dataflow synthesis
  with HDL interchange format
• Language-based general purpose tool
• Languages Verilog, VHDL, C, APL, ISP
• Scheduling is the core activity
• Create states and assign operations to states
• Allocation
• Operations assign to hardware and data to storage
  elements
• Trade off latency for area and register area for
  combinational and interconnect area
• Optimized design advantages over RTL synthesis

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RTL Synthesis

• State graph states and transitions are tightly
  bound to resources
• Serve as a back end for other synthesis (but it
  can be a front-end tool in its own right)
• Cumbersome, verbose and error prone
• Logic synthesis
• Propagation delay and area optimization
• Back end for higher abstraction

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Simulation and Verification

• Simulation tests the response for particular
  inputs
• Formal verification mathematically proves
  equivalence between the design and a golden
  model described by math properties
• E.g., a design is deadlock free, against Boolean
  expressions and specific functions
• Design verification checks properties
• Implementation verification checks, e.g., an
  optimized version against un-optimized version
• They work well with combinational logic but the
  problem is very difficult for design with states,
  e.g., under process statements

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RTL and Behavioral Design

• Behavioral synthesis tools glue the
  domain-specific and RTL synthesis tools, e.g., C
  description to the dataflow oriented
  toolx0while (!reset) u read(input) x
  ax bu write(output)
• Initial questions on data widths, operation
  ordering, rounding methods, timing, states and
  queue sizes are abstracts in terms of C or C
• This abstract model is translated to HDL model
  where interfaces and timing between modules are
  corrected using simulation

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RTL and Behavioral Design continued

• Synthesizable description
• Processes are synthesized into separate FSMs or
  logic blocks. They may be connected by logic
  blocks.
• The number of states in behavioral synthesis can
  be optimized and operations assigned to states
  can also changes post optimization
• In RTL synthesis, the design decide on the FSM
  design

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a
x1


b
u


x
lt

• Schedule example xk axk-1 buk

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a
x1
mux

u
b

R



x

• Allocation xk axk-1 buk

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Behavioral Compiler Flow

• HDL input simulate
• 1. HDL analysis (parsing and semantic analysis)
  and elaboration for scheduling
• 2. User constraints
• Timing model of the dataflow portion
• Explicit user constraints, e.g., number of clock
  cycles
• Dataflow -gt gate-level netlist -gt target
  technology
• Early timing analysis (technology-specific
  scheduling)
• 3. Schedule
• Assignment of operations to states

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Behavioral Compiler Flow Continued

• 4. Allocate
• Modules and registers are constructed
• Mapping from the logical operations and data to
  netlist modules and registers
• Outputs a logical description of the
  datapath-abstract resources and data transfer
• 5. Build netlist and control FSM
• Simulation
• 6. Logic-level optimization constraints and
  report
• Timing-accurate timing simulation, testability
  assertion, test generation and layout
• EDIF or others output