Life With and After CMOS: Towards Hybrid CMOSSET IC Architectures

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Life With and After CMOS Towards Hybrid CMOS-SET
IC Architectures?
Adrian M. Ionescu Electronics Laboratories
Institute of Microelectronics and Microsystems
Swiss Federal Institute of Technology
Lausanne Contact Adrian.Ionescu_at_epfl.ch
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Outline

• Introduction
• Pushing CMOS the 10 nm wall
• (Micro)electronic switch with and after CMOS
• Single Electron Transistors
• Digital SET circuits
• to mimic or not to mimic CMOS?
• Hybrid CMOS-SET Architectures
• illusion or useful compromise?
• Applications à ultra low power CMOS-SET ICs
• Conclusion and perspectives

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CMOS past and future
Alternative devices
CMOS
100
CMOS IC evolution
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1
CMOS
Feature Size (mm)
0.1mm in 2002
0.1
0.01
Transition Region
Alternative devices
Quantum devices
0.001
Atomic dimensions
1960
2000
2020
2040
1980
Year
After J.D. Plummer, Proceedings of IEEE, 2001.
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ITRS close to 10nm wall

• International Technology Roadmap for
  Semiconductors
• revisions and accelerations à 2001/1997 4-year
  shift

After J. Gautier, LETI-CEA, private communication.
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CMOS 15nm channel length
Key problems of MOSFET for sub-10nm channel length
(i) electrostatic limits (ii) source-to-drain
tunnelling (iii) carrier mobility (iv) process
variations (v) static leakage (vi) Power density
Emerging architectures

• Double- and Multi-gate MOSFETs
• Fin-FET
• vertical MOSFET
• ballistic transistor

Intel's 15 nm channel length MOSFET Courtesy of
George Sery, Intel Corporation, Santa Clara,
USA.
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Life with and after CMOS
(micro-)electronic switch
After CMOS
With CMOS
Aggressively miniaturized CMOS emerging devices
Quantum nanoelectronic devices
HYBRID ICs
Molecular electronics
Solid state nanoelectronic devices
Small conductive molecules
Quantum dots
Spin transistor
Carbon nanotubes
SETs SEMs
RSFQ
RTDs
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Single Electron Transistor versus conventional
MOSFET

• electron conduction is one by one
• drain/gate controls Coulomb blockade
• needs opaque junctions
• RT gt RQ26kW
• needs very small island (nm)

• many electrons simultaneously
• participate to conduction
• gate controls channel
• junctions highly transparent

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How SET works?

• Charging energy of the island larger than
  thermal fluctuations

• Quantum mechanical uncertainty
• of electron location covered up

• Typical current oscillations with VG

• low VD current suppression called
• Coulomb Blockade

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Operation _at_ room temperature

• Kiriharas criteria
• island capacitance
• lt0.2aF
• island diameter
• 1nm

Tmaxlt e2/40kCS
PADOX, VPADOX
Key challenges for SET technology CMOS
compatibility
undulated nanograin polysilicon
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SET inverter to mimic or not to mimic CMOS?
Key features

• needs 2 devices of SAME type (SET)
• power dissipation is essentially static
• Ultra-Low Power
• 10-8-10-10W
• 5 decades lower than CMOS!
• very sensitive to T works under Coulomb
  blockade

Current 10pA-10nA, Voltage 1-100mV
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Why hybrid CMOS-SET?
Uchida et al., ISSCC 2002

• à SET key advantages
• ultra-small (nm)
• ultra-low consumption
• (5 decades better than CMOS)
• new functionality
• could be combined with CMOS

à CMOS and SET are COMPLEMENTARY à CMOS advantage
can compensate SET disadvantage
- low driving capability - high output
impedance - small VDS
high driving capability high input
impedance high voltage gain
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CMOS/SET for communication applications

• Hybrid CMOS-SET architectures higly interesting
  for
• ultra-low power communication appplications
• Quantizers
• Negative Differential Resistance (NDR) circuits

NTTs
EPFLs
EPFLs NDR
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Future ULSI hybrid CMOS/SET architectures
System design
robustness, fault tolerance, complex functions,
reconfigurability
Novel device funtionality, inherent lack of
accuracy, ultra-low power, high density
Research strategy should be adapted
Bottle neck
SET device level
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Conclusion

• Progress in microelectronics has pushed device
• dimensions towards sub-10nm limits
• à impact on the basic physical principles of
  MOSFETs
• MOSFETs will need to share their domination on
• modern ICs with new device architectures
• à Single Electron Transistors ?
• Important CMOS and SET are complementary and
• NOT in competition à replacement strategy is
  wrong!
• à SET champion of low-power new
  functionality
• à CMOS high speed, high driving
• à Applications that can benefit from
  ultra-low power communications
• 3-level effort needed for success of hybrid
  CMOS/SET
• (I) development of CMOS-SET technological
  platform
• (II) enable advanced SET/CMOS co-simulation
  and design
• (III) innovation on new functionality of
  hybrid IC architectures,
• tolerant to background charge effects