Design Productivity Crisis

1
Futures for DSM Physical Implementation Where
is the Value, and Who Will Pay?
Andrew B. Kahng abk_at_cs.ucla.edu ,
http//vlsicad.cs.ucla.edu UCLA Computer Science
Department 12th DA Show, Tokyo July 14, 2000
2
(No Transcript)
3
Subwavelength Optical Lithography
Subwavelength Gap since .35 ?m
Numerical Technologies, Inc.
4
The Design Productivity Gap
Potential Design Complexity and Designer
Productivity
Equivalent Added Complexity
Logic Tr./Chip Tr./S.M.
68 /Yr compounded Complexity growth rate
21 /Yr compound Productivity growth rate

How many gates can I get for N?
3 Yr. Design
Year Technology Chip Complexity
Frequency Staff Staff Cost

• 250 nm 13 M
  Tr. 400 MHz 210
  90 M
• 250 nm 20 M
  Tr. 500 270
  120 M
• 180 nm 32 M
  Tr. 600 360
  160 M
• 2002 130 nm 130
  M Tr. 800 800
  360 M

Source SEMATECH
_at_ 150 k / Staff Yr. (In 1997 Dollars)
5
Outline

• Future DSM physical implementation technologies
• design closure
• design-manufacturing interface
• Valuations
• the significance of design productivity and
  design quality
• structural aspects of the EDA industry
• Values
• toward maturity and a design productivity
  renaissance
• Conclusions Who Will Pay ?

6
Outline

• Future DSM physical implementation technologies
• design closure
• design-manufacturing interface
• Valuations
• the significance of design productivity and
  design quality
• structural aspects of the EDA industry
• Values
• toward maturity and a design productivity
  renaissance
• Conclusions Who Will Pay ?

7
What is design closure?
front end consistent with back end
meet constraints here Û meet
constraints there
What is the problem ?
source K. Keutzer, DAC 2000
8
Design closure predicting interconnect
9
Aristo, DAC-2000 panel
Olympic Flame
TYPICAL DESIGN FLOW
Design Constraints
IP Blocks
Library
Design Netlist
Gate-Level Verilog
Concurrent Block Partitioning, Clustering
Placement
Early Planning
Gate-Level Optimization
Design Refinement
Gate-Level Place Route
Top-Level Routing
Chip Assembly
RC Extraction
Timing Analysis
PREDICTABLE HIERARCHICAL DESIGN CONVERGENCE
10
Recycle Bin
Physical Prototyping
Design Signoff
GDSII
Monterey, DAC-2000 panel
11
Anakin Skywalkers Pod Racer
3D Extraction
Prepare
Database
Timing Sign-off
Delay
True-3D
Calculation
Parasitics
Place
Timing
Timing
Sequence
RTL

Synthesis
Analysis
Analysis
Route
Interconnect
Interconnect
Driven
Driven
Optimization
Optimization
Driver sizing,topology-based optimization
Sequence, DAC-2000 panel
12
Clear Thinking Basics of Design Convergence

• What must converge ?
• logic, timing, and spatial embedding
• support front-end signoff, provide predictable
  back-end
• Ways to achieve Convergence through
  Predictability
• correct by construction (assume, then enforce)
• constraints and assumptions passed downstream
  not much goes upstream
• ignores concerns via guardbanding
• separates concerns as able (e.g., FE logic/timing
  vs. BE spatial embedding)
• construct by correction (tight loops)
• logic-layout unification synthesis-analysis
  unification, concurrent optimization
• elimination of concerns
• reduced degrees of freedom, pre-emptive design
  techniques
• e.g., power distribution, layer assignment /
  repeater rules, GALS/LIS

13
What Must A Design Closure Tool Look Like ?

• Input
• RT-level HDL technology constraints
• Output
• go recipe for invocation and composition of
  commodity SPR
• no go diagnosis of RTL code problems
• Logical and physical hierarchies co-evolve
• spatial top-down coarse placement ? physical
  hierarchy
• logic/timing implementable RTL ? logical
  hierarchy
• limits of human fanout, organizations ? always
  have hierarchy
• natural sequence of no-floorplanning,
  phys-floorplanning, RTL-floorplanning...
• Details (must construct, predict, ignore,
  eliminate, ...)
• pin optimizations, interconnect planning,
  hierarchy reconciliations, budgeting mechanisms,
  compatibility with downstream SPR, ...

14
DONT Develop This RTL Planning Technology

• Dont spend too much time packing blocks that
  will change
• goal early diagnosis, or handoff to commodity
  SPR
• pre-synthesis uncertainty /- 15 area,
  timing
• wirelength, path timing must be
  connectivity-centric, not packing-centric
• easier to work on direct realizations of the
  floorplan, not representations
• need relative coarse placement that adapts to
  incremental ECOs
• Dont over-constrain block shaping (rectangles,
  Ls, Ts)
• placers handle constraints w/ granularity site
  spacing, row height
• constructive pin assignment dont need
  roundness
• path timing optimization may even want
  disconnected shapes
• Dont under-constrain layout region
• fixed-die planning simultaneous
  zero-whitespace, zero-overlap

15
Do Allow the Following...
1.0
0.5,0.5
1.0
Blk A
Blk B
16
It Is What the Cells Want Anyway !
17
Do Develop This RTL Planning Technology

• RTL partitioning
• understand interaction b/w block definition and
  placement quality
• recognize and cure a physically challenged logic
  hierarchy
• Global interconnect planning and optimization
• symbolic route representations to support block
  plan ECOs
• Controllable SPR back end (including
  power/clock/scan)
• Incremental / ECO optimizations, and
  optimizations that are robust under partial or
  imperfect design knowledge
• Better estimators (initial WLMs)
• to account for resource, topological
  heterogeneity
• to account for optimizations (placement,
  ripup/reroute, timing)
• ? earliest RTL signoff with detailed PR
  knowledge

18
Conclusion

• RTL-to-GDSII will commoditize SPR market sectors
• Many solutions are reasonable and will survive in
  the marketplace ? RTL-down SPR
  becomes a commodity
• No solution is complete
• Key missing pieces include RTL partitioning
  hierarchy and block management real working RTL
  diagnosis and signoff
• Individual point technologies (e.g., global
  placement or detailed routing) become less
  valuable ? integration is most important

19
Outline

• Future DSM physical implementation technologies
• design closure
• design-manufacturing interface
• Valuations
• the significance of design productivity and
  design quality
• structural aspects of the EDA industry
• Values
• toward maturity and a design productivity
  renaissance
• Conclusions Who Will Pay ?

20
Subwavelength Optical Lithography
Subwavelength Gap since .35 ?m
Numerical Technologies, Inc.
21
Optical Proximity Correction (OPC)

• Corrective modifications to improve process
  control
• improve yield (process window)
• improve device performance

22
Future OPC-Related Technologies

• WYSIWYG broken (mask) verification bottleneck
• Function-aware OPC insertion
• OPC insertion is for predictable circuit
  performance, function
• tool understands functional intent, makes only
  the corrections that win , reduce performance
  variation
• applies to mask inspection as well
• OPC- and manufacturing-aware layout
• dont make corrections that cant be manufactured
  or verified
• model effects of geometry on OPC cost needed to
  yield function
• understand (data volume, verification) costs of
  breaking hierarchy
• Difficult solutions to flow issues
• e.g., how to avoid making same corrections 3x
  (library, router, PV)

23
Phase Shifting Masks (PSM)
24
Double-Exposure Bright-Field Alternating PSM

• Positive photoresists for poly, metal
  ? unexposed areas
  printed features

0


180
180
25
Why is Alternating PSM Valuable and Essential ?

• PSM enables smaller transistor gate lengths Leff
• critical polysilicon features only (gate Leff)
• faster device switching faster circuits
• better critical dimension (CD) control better
  parametric yield, /wafer
• Full-chip PSM (poly, local interconnect) ? denser
  layouts
• smaller die area more /wafer
• achieving Roadmap for device density depends on
  PSM
• Data points
• 25 nm gates manufactured with 248nm DUV steppers
  (NTI MIT Lincoln Labs, June 2000)
• 90nm gates in production at Motorola, Lucent
  since 1999
• Alternative 5 B fab with equipment that
  doesnt exist yet

26
The Phase Assignment Problem

• Assign 0, 180 phase regions such that critical
  features with width lt B are induced by adjacent
  phase regions with opposite phases

0
180
27
Key Global 2-Colorability

• Odd cycle of phase implications layout
  cannot be manufactured
• layout verification becomes a global, not local,
  issue

?
180
0
180
0
180
180
28
Critical features F1,F2,F3,F4
F2
F4
F1
F3
29
F2
F4
F1
F3
Opposite-Phase Shifters (0,180)
30
F2
S3
S4
F4
S7
S8
S1
F1
S2
F3
S5
S6
Shifters S1-S8

• PROPER Phase Assignment
• Opposite phases for opposite shifters
• Same phase for overlapping shifters

31
F2
S3
S4
F4
S7
S8
S1
F1
S2
F3
S5
S6
Phase Conflict
Proper Phase Assignment is IMPOSSIBLE
32
Phase Conflict Resolution
F2
S3
S4
F4
S7
S8
S1
F1
S2
F3
S5
S6
Phase Conflict
feature shifting to remove overlap
33
Phase Conflict Resolution
F2
S3
S4
F4
S7
S8
S1
F1
S2
F3
Phase Conflict
feature widening to turn conflict into
non-conflict
34
Future PSM-Related Technologies

• UCLA-Cadence first comprehensive methodology
  for AltPSM layout design
• 3-way shared responsibility for
  phase-assignability
• good layout practices (local geometry)
• no T shapes, no doglegs, even-length transistor
  fingers, ...
• but no complete set of rules exists
• automatic phase conflict resolution (global
  2-colorability)
• latest technology optimal conflict resolution
  for 50K polygons in 6 sec
• reuse of layout (free composability)
• problem guarantee reusability of phase-assigned
  layouts, such that no odd cycles can occur when
  the layouts are composed together in a larger
  layout
• Changes all flows library design, custom
  design, SPR

35
Macroscopic Process Effects
Dummy Fill controls several types of process
distortions
CMP, SOG
RIE
CVD
R. Pack, Cadence
36
Field-Dependent Aberration

• Field-dependent aberrations cause placement
  errors and distortions

R. Pack, Cadence
37
Conclusions

• RTL-to-GDSII commoditizes existing SPR market
  sectors
• Design-manufacturing interface will change EDA
• Closely related to foundry capital expenditure
• Unites EDA with much of mask industry, even
  process development
• Expands scope of physical verifications, moves
  awareness upstream into syntheses (logic,
  layout)
• Very comprehensive changes to data model,
  infrastructure, flows
• Unified, front-to-back solutions will win

38
Outline

• Future DSM physical implementation technologies
• design closure
• design-manufacturing interface
• Valuations
• the significance of design productivity and
  design quality
• structural aspects of the EDA industry
• Values
• toward maturity and a design productivity
  renaissance
• Conclusions Who Will Pay ?

39
The Productivity Gap
Potential Design Complexity and Designer
Productivity
Equivalent Added Complexity
Logic Tr./Chip Tr./S.M.
68 /Yr compounded Complexity growth rate
21 /Yr compound Productivity growth rate

How many gates can I get for N?
3 Yr. Design
Year Technology Chip Complexity
Frequency Staff Staff Cost

• 250 nm 13 M
  Tr. 400 MHz 210
  90 M
• 250 nm 20 M
  Tr. 500 270
  120 M
• 180 nm 32 M
  Tr. 600 360
  160 M
• 2002 130 nm 130
  M Tr. 800 800
  360 M

Source SEMATECH
_at_ 150 k / Staff Yr. (In 1997 Dollars)
40
Mask Cost
But average only 500 wafers per mask set !
41
Keep the Fabs Full

• Design technology must keep manufacturing
  facilities fully utilized with
• high-volume parts
• high-margin parts
• Foundry capital cost gt 2B
• How much value of new designs is needed to fill
  the fab ???

42
Design Productivity Need DSM
2 EDA Trends
source MARCO GSRC
43
Fab Amortization ? Close the Implementation Gap
Level of Abstraction
Effort/Value
source MARCO GSRC
44
Design Productivity Gap ? Low-Value Designs?
Percent of die area that must be occupied by
memory to maintain SOC design productivity
Source Japanese system-LSI industry
45
Reduce Back-End Effort ?
Example repeating dense wiring fabric pattern
at minimum pitch
- Eliminates signal integrity, delay uncertainty
concerns - But has at least 60 - 80 density cost
source MARCO GSRC
46
Improve IP Reuse Productivity ?
source MARCO GSRC
47
QUALITY Problem gt 1000x Energy-Flexibility Gap
1000
100-200 MOPS/mW
Dedicated HW
100
10-50 MOPS/mW
ReconfigurableProcessor/Logic
Energy Efficiency MOPS/mW (or MIPS/mW)
10
ASIPs DSPs
1 V DSP 3 MOPS/mW
1
Embedded mProcessors
LP ARM 0.5-2 MIPS/mW
0.1
Flexibility (Coverage)
Source Prof. Jan Rabaey, UC Berkeley
48
Keep the Fabs Full

• Design technology must keep manufacturing
  facilities fully utilized with
• high-volume parts
• high-margin parts
• What happens when design technology fails ?
• not enough high-value designs
• ? the semiconductor industry will find a
  workaround
• reconfigurable logic
• platform-based design

49
Platform-Based Design
source MARCO GSRC
50
Conclusions

• RTL-to-GDSII commoditizes existing SPR market
  sectors
• Design-manufacturing interface will change EDA
• Design productivity gap threatens design quality
  ? ASIC business model is at
  risk
• TAT achieved at cost of QOR
• low QOR ? low silicon value
• electronics industry chooses reprogrammable,
  platform-based workarounds

51
Outline

• Future DSM physical implementation technologies
• design closure
• design-manufacturing interface
• Valuations
• the significance of design productivity and
  design quality
• structural aspects of the EDA industry
• Values
• toward maturity and a design productivity
  renaissance
• Conclusions Who Will Pay ?

52
EDA Industry Structure Vendor Side

• Tool usage focus still the core of the business
  model
• slows down the move to open systems, open
  infrastructure
• Some indicators of immaturity
• lack of metrics and other common infrastructure
• LEF/DEF, SPEF, SPF, OLA, .lib, ... are a
  minimal start, were slow to develop
• no differentiation between strategic, commodity
  technology
• Some indicators of poor health
• customer integration investment is 2.5x - 4x
  times tool investment
• EDA RD 20 of revenue, but 80 of RD
  support, infrax
• RD often provided by customers (designers),
  outsourced (MA)

53
EDA Industry Structure Customer Side

• Collectively, insist that EDA be everything to
  everyone
• fragmentation of vendor RD resource, lots of
  secret options, ...
• tools attempt to fit in all methodologies fit
  in none
• Wont let EDA vendors evolve to a more
  sustainable model
• push for low ASPs while spending 4x on
  integration low RD levels
• sometimes invest in fragmentation of RD talent
  (20 SPR, 70 verif startups)
• No differentiation between strategic, commodity
  technology
• one-offs, hidden options
• very little cooperative foundation e.g., data
  model API, silicon calibration, library char,
  RLC extraction, gate/int delay calc, STA,
  physical verification

54
Must Escape Death Spiral

• Failure of EDA
• why pay for it
• why invest in it
• why work on it
• ...
• Must stop wasting scarcest of all resources
  brains
• how many GDSII parsers do we need ? how many
  interconnect delay calculators ? how many
  netlist connectivity data models ?
• acknowledge de facto commodity technology
• turn these technologies into common
  infrastructure
• Mature behavior is required
• with respect to strategic vs. commodity
  distinction
• with respect to control

55
Conclusions

• RTL-to-GDSII commoditizes existing SPR market
  sectors
• Design-manufacturing interface will change EDA
• Design productivity gap threatens design quality
• EDA industry must evolve and mature to achieve
  EDA industry productivity
• eliminate wastage on duplicated commodity
  infrastructure
• acknowledge and share de facto commodity
  technologies

56
Outline

• Future DSM physical implementation technologies
• design closure
• design-manufacturing interface
• Valuations
• the significance of design productivity and
  design quality
• structural aspects of the EDA industry
• Values
• toward maturity and a design productivity
  renaissance
• Conclusions Who Will Pay ?

57
CAD Life Cycle Questions

• What will the design problem look like?
• How can we quickly develop the right design
  technology?
• Did I really solve the problem?
• Did the design process improve?
• Did achievable design envelope get bigger?
• Proposal We MUST develop shared infrastructure
  to answer all three questions

58
1. Technology Extrapolation
What is the most power-efficient noise management
strategy?

• Evaluates impact of
• design technology
• process technology
• Evaluates impact on
• achievable design
• associated design problems
• Questions to be addressed
• What will the design problem look like ?
• Sets requirements for CAD tools, methodologies,
  investment
• Familiar example ROADMAPS

How and when do L, SOI, SER, etc. matter?
Will layout tools need to perform process
simulation to effectively model cross-die and
cross-wafer manufacturing variation?
59
Optimal Repeater Sizing

• Most commonly used optimal repeater sizing
  expression (Bakoglu)
• New study
• Sweep repeater size for single stage in the chain
  
• Examine both delay and energy-delay product

60
Cu Resistivity Effect of Line Width Scaling
ITRS 1999 Line width (nm)
280 170 133
Global Semiglobal Local
525 320 250
95 58 48
Effect of 5 nm Barrier
Effect of Electron Scattering

• Conformal 5 nm barrier assumed
• Even a 5 nm barrier will increase resistivity
  drastically

• No barrier assumed
• Electron scattering increases resistivity
• Lowering temperature has a big effect

source MARCO IFRC
61
Cu Resistivity Barriers Deposition Technology
Atomic Layer Deposition (ALD) Ionized
PVD Collimated PVD

• 5 nm barrier assumed at the thinnest spot
• No scattering assumed, I.e., bulk resistivity

Interconnect dimensions scaled according to ITRS
1999
source MARCO IFRC
62
What Technology Extrapolation is Available Today?

• Too many Roadmaps
• ITRS, JISSO, STARC, Roadmaps
• some university tools SUSPENS, GENESYS, RIPE,
  BACPAC,
• numerous tools in industry
• Observations
• everyone predicts same parameters but different
  assumptions, inputs near-total duplication of
  effort !!!
• no documentation or visibility into internal
  calculations
• hard-wired ? cannot easily test other modeling
  choices
• missing models of CAD tools and optimizations
  (what is really achievable?)
• missing scope, comprehensive coverage

63
Shared, Worldwide Technology Extrapolation System

• Flexibility
• edit or define new parameters and relations
  between them
• perform specific studies (but different studies
  at different times)
• Quality
• continuous improvements
• world-wide participation of experts
• Transparency
• open-source mechanism
• models visible to the user
• No more redundant effort
• permanent repository of first choice
• adoptability and maintainability

64
GTX GSRC Technology Extrapolation System

• GTX is set up as a framework for technology
  extrapolation
• Living Roadmap
• Open-source http//vlsicad.cs.ucla.edu/GSRC/GTX
  /

65
2. CAD-IP Reuse

• How can we quickly develop the right design
  technology?
• Problem Currently takes 5-7 years to get a
  leading-edge algorithm into production tools
• Result Must solve todays design problems with
  yesterdays CAD technology
• Problem Published descriptions insufficient for
  replication or even comparison of algorithms
• Result Cannot identify, evaluate or advance the
  CAD technology leading edge
• IF WE DO NOT KNOW WHERE THE LEADING EDGE OF CAD
  TECHNOLOGY IS, WE HAVE A REAL PROBLEM !!!

66
Unclear Leading Edge of CAD A Real Problem

• Comparison of two LIFO-FM partitioner
  implementations
• Min and Ave cut sizes from 100 single-start
  trials
• Papers 1, 2 both published since mid-1998
• This is a crisis !

67
2. CAD-IP Reuse

• How can we quickly develop the right design
  technology?
• Problem Currently takes 5-7 years to get a
  leading-edge algorithm into production tools
• Result Must solve todays design problems with
  yesterdays CAD technology
• Problem Published descriptions insufficient to
  enable replication or even comparison of
  algorithms
• Result Cannot identify, evaluate or advance the
  CAD technology leading edge
• The TAT and QOR problems are not only for CAD
  customers, but for CAD itself !!!
• productivity of CAD tool development
  (time-to-market)
• quality of resulting CAD tools (quality-of-result)

68
Analogy Hardware Design CAD Tool Design

• Hardware design is difficult
• complex electrical engineering and optimization
  problems
• mistakes are costly
• verification and test not trivial
• few can afford to truly exploit the limits of
  technology
• A Winning Approach Hardware IP reuse
• CAD tools design is difficult
• complex software engineering and optimization
  problems
• mistakes can be showstoppers
• verification and test not trivial
• few can manage complexity of leading-edge
  approaches
• A "Surprising Proposal CAD-IP reuse

69
What is CAD-IP?

• Data models and benchmarks
• context descriptions and use models
• testcases and good solutions
• Algorithms and algorithm analyses
• mathematical formulations
• comparison and evaluation methodologies for
  algorithms
• executables and source code of implementations
• leading-edge performance results
• Traditional (paper-based) publications

70
The Bookshelf A Repository for CAD-IP

• Community memory for CAD-IP
• data models
• algorithms
• implementations
• Publication medium that enables efficient CAD RD
• benchmarks, performance results
• algorithm descriptions and analyses
• quality implementations (e.g., open-source UCLA
  PDTools)
• Simplified comparisons to identify best
  approaches
• Easier for industry to communicate new use models
• http//vlsicad.cs.ucla.edu/GSRC/bookshelf

71
Proposed Change for Entire EDA Community

• Proposal Data model and API are
  non-competitive and non-differentiating
• Genesis, MilkyWay, CHDStd-IDM, UDM-Nike, all
  very similar !
• should be commoditized and shared by the
  community
• coopetition distributes infrastructure burden,
  frees RD resources
• coopetition cooperation competition
• ? Common data model across multiple vendors,
  users
• common API is necessary common database is not
  necessary
• control issues solved by open-source model
  (www.openeda.org)
• issues of integration and adoption costs still to
  be overcome

72
3. METRICS

• Did I really solve the problem?
• Foundation of design optimization
• understanding of what should be optimized by
  which heuristic
• understanding of design as a process
• There are no standards or infrastructure for
  measuring and optimizing the semiconductor design
  process
• METRICS measure, then improve
• design becomes less of an art and more of a
  formal discipline
• Infrastructure
• design process data collection infrastructure
• data mining / visualization / diagnosis
  infrastructure

73
METRICS System Architecture
74
Benefits of METRICS

• Benefits for project management
• accurate resource prediction at any point in
  design cycle
• up front estimates for people, time, technology,
  EDA licenses, IP re-use...
• accurate project post-mortems
• everything tracked - tools, flows, users, notes
• no loose, random data left at project end
• management console
• web-based, status-at-a-glance of tools, designs
  and systems at any point in project correct
  go / no-go decisions as early as possible
• Benefits for tool RD
• feedback on tool usage and parameters used
• real benchmarking

75
Example Diagnoses

• Placer runtime is linear in number of cells ?
  GOOD !
• CPU_TIME 12 0.027 NUM_CELLS (corr 0.93)
• Placer runtime becomes unpredictable at two
  particular utilization thresholds ? BAD !
• 80, 95

76
The Industry Needs METRICS Standards

• Standard metrics naming across tools
• same name same meaning, independent of tool
  supplier
• generic metrics and tool-specific metrics
• no more ad hoc, incomparable log files
• Standard schema for metrics database
• Standard middleware for database interface
• See http//vlsicad.cs.ucla.edu/GSRC/METRICS

77
CAD Life Cycle Questions

• What will the design problem look like?
• answer technology extrapolation
• How can we quickly develop the right design
  technology?
• answer CAD-IP reuse
• Did I really solve the problem?
• Did the design process improve?
• Did achievable design envelope get bigger?
• answer Metrics

78
Conclusions

• RTL-to-GDSII commoditizes existing SPR market
  sectors
• Design-manufacturing interface will change EDA
• Design productivity gap threatens design quality
• EDA industry must evolve and mature to achieve
  EDA industry productivity
• Open, shared infrastructure can restore TAT, QOR
  of design technology
• 3 initiatives Technology Extrapolation, CAD-IP
  Reuse, and METRICS

79
Outline

• Future DSM physical implementation technologies
• design closure
• design-manufacturing interface
• Valuations
• the significance of design productivity and
  design quality
• structural aspects of the EDA industry
• Values
• toward maturity and a design productivity
  renaissance
• Conclusions Who Will Pay ?

80
We Must Solve the CAD Productivity Challenges

• Death Spiral is a bad local optimum
  configuration
• not enough value, not enough RD, fragmentation
  of RD
• The design quality gap is just as dangerous as
  the design productivity gap
• ASIC business model is at risk !
• Solution lies in maturity of the EDA industry
• coopetitive behavior of vendors and customers,
  together

Future
Today
Happiness
81
We Will Solve the CAD Productivity Challenges

• Build the non-differentiating, open-source EDA
  foundation
• Bottom Up data model (API), concrete syntax
  (e.g., .lib XML), tech extrapolation,
  silicon calibration/characterization, performance
  analyses, ...
• EDPS, CHDStd, DAPIC experiences useful
  foundation
• world-wide cooperation needed (Japan/Asia, North
  America, Europe)
• Understand that bottom-up commoditization of
  tools and adapters is inevitable
• Bottom Up Analyses first (RCX, DC, STA), then
  Syntheses (S, P R)
• pure tools static (?), but value remains in
  being best at leading edge
• enormous resource savings in duplicated RD,
  maintenance
• more value from integrations, methodologies,
  faster technology delivery
• Long-term EDA moves upward in value chain
• escapes service role
• becomes more aware, specific to markets,
  manufacturing process

82
Who Will Pay?

• Costs of cooperating are less than costs of not
  cooperating
• Benefits of cooperation are immense
• free up brains to improve Design Technology TAT
  and QOR
• technology extrapolation CAD-IP reuse Metrics
  delivery of
  solutions the right problems, at the right time,
  with measurable impact
• We should welcome costs of openness, shared
  infrastructure
• academia, vendor internal EDA, designer
  communities together
• It is a great future, if we make it happen !

83
THANK YOU !
84
EXTRA SLIDES
85
Synergies
Estimates of best-optimized
design, optimal tradeoffs
Feasibility / sanity checkers to embed within a
tool flow
GTX
Which problems are critical? What
will instances look like?
Optimized design processes, calibration data for
modeling CAD optimization
CAD-IP Reuse
Metrics
Models, measures of algorithmic activity
Objective functions, tool QOR metrics
86
GTX Engine

• Contains no domain-specific knowledge
• Evaluates rules in topological order
• Performs studies
• Multiple values through sweeping
• Runs on three platforms (Solaris, Windows and
  Linux)

87
GTX Graphical User Interface (GUI)

• Provides user interaction
• Visualization (plotting, printing, saving to
  file)
• 4 views
• Parameters
• Rules
• Rule chain
• Values in chain

88
The World of the Living Roadmap
Technology Models
The Internet
Sematech, GSRC The Golden Copy
Richard Newton
89
Challenges for Applied Algorithmics

• Research in mature areas can stall
• incremental research - difficult and risky
• implementations not available ? duplicated effort
• too much trust ? which approach is really the
  best?
• some results may not be replicable
• not novel is common reason for paper rejection
• exploratory research - paradoxically, lower-risk
• novelty for the sake of novelty
• yet, novel approaches must be well-substantiated
• Pitfalls questionable value, roadblocks,
  obsolete contexts

90
What Are Some Concrete, Industry-Wide Steps?

• First step open minds
• Second step agreements on scope of design
  activity
• bound the interoperability problem by defining
  canonical design states, e.g.
• cycle-accurate microarchitecture
• gate-level placement
• global-routed but not detailed-routed
• Third step proofs that coopetition is feasible
• how different or similar are (for example)
• foundry process/rule description formats?
  library model generators?
• IDM/CHDStd, UDM, Genesis, MilkyWay, ...?
• AWE, ramp-Elmore, etc. interconnect delay
  calculations?

91
Where is the Solution ? (DAC-2000 Panel)
A RTL estimation B RTL synthesis
optimization C gate-level estimation D
gate-level logic optimization E cell wire
sizing physical support (e.g., PR) F block
placement, floorplanning wireplanning
budgeting G gate-level place and route H other
92
Perfect Rectilinear Floorplanning

• Fixed-die planning find a coarse global
  floorplan, then migrate whitespace overlap such
  that both disappear

93

• See, for example http//vlsicad.cs.ucla.edu/SL
  IP2000/

Kn
Mn
94
What Does Process Variability Imply for EDA ?

• VERY DIFFICULT PROBLEMS !
• We require much deeper understanding of process
• coma effects (lens aberration)
• halation (iso-dense effects on etch dynamics)
• statistical variation in ion implant
• Performance verification infrastructure may
  change
• E.g., delay is no longer a number it is a
  distribution
• Must have complete, integrated, front-to-back
  solutions
• All three examples OPC, PSM, Area Fill
• Long-term must drive process requirements from
  system architecture and design technology roadmaps

95
RC and RLC Interconnect Delay Models

• Five different interconnect models
• Bakoglus model (RC)
• Alpert, Devgan and Kashyap, ISPD 2000 (RC)
• Ismail, Friedman and Neves, TCAD 19(1), 2000
  (RLC)
• Kahng and Muddu, TCAD 1997 (RLC)
• Extension of Alpert, Devgan and Kashyap, ISPD
  2000 (RLC)

96
Generic and Specific Tool Metrics
Partial list of metrics now being collected in
Oracle8i
97
Example Testbed Cadence SLC Flow
M E T R I C S
DEF
Placed DEF
Incr.
LEF GCF,TLF
Clocked DEF
Constraints
Optimized DEF
Routed DEF
98
Current Status of METRICS Initiative

• Current status
• complete prototype of METRICS system with
  Oracle8i, Java Servlet, XML parser, and
  transmittal API library in C
• METRICS wrapper for Cadence and Cadence-UCLA
  flows, front-end tools (Ambit BuildGates and
  NCSim)
• easiest proof of value via use of regression
  suites
• Issues for METRICS constituencies to solve
• security proprietary and confidential
  information
• standardization flow, terminology, data
  management, etc.
• social big brother, collection of social
  metrics, etc.
• Ongoing work with EDA, designer communities to
  identify tool metrics of interest
• users metrics needed for design process
  insight, optimization
• vendors implementation of the metrics
  requested, with standardized naming / semantics

99
GTX Current Status

• Models implemented
• cycle-time models of SUSPENS (with extension by
  Takahashi), BACPAC (Sylvester, Berkeley), Fisher
  (ITRS)
• currently adding
• GENESYS (with help from Georgia Inst. Tech.)
• RIPE (with help from Rensselaer Univ.)
• new device and power modules (Synopsys /
  Berkeley)
• new SOI device model (Synopsys / Berkeley)
• inductance models (Silicon Graphics / Berkeley /
  Synopsys)
• yield and die cost models (CMU)
• Studies performed in GTX
• model and parameter sensitivity analyses
• design optimization studies
• Seeking contributions, suggestions of new models,
  studies