Delevopment Tools Beyond HDL

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Delevopment Tools Beyond HDL
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Overview

• Introduction
• FPGA Design Challenges
• VHDL
• Tools with higher abstraction level
• Handel-C
• Features
• Differences to VHDL
• Advantages
• Drawbacks
• Possible applications

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Common Prejudice ..

• FPGAs are good for applications which
• involve simple algorithms which can be executed
  in parallel
• require high speed (few ns level) response to
  real time events
• do not need frequent redesigns (expert knowledge
  required !)
• DSPs are good for applications which
• involve complex algorithms with many arithmetic
  operations
• are less demanding in real time requirements
• require programming in C / C because sometimes
  even a physicst needs to change part of the code

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FPGA / DSP Performance (3/2003)

• Example XILINX Virtex-II and Virtex-II Pro

Function Industrys Fastest DSP Processor Core Xilinx Virtex-II Virtex-II Pro
8 x 8 Multiply Accumulate (MAC) 4.8 billion MAC/s 0.5 Tera MAC/s 1 Tera MAC/s
FIR Filter - 256 taps, linear phase - 16-bit data/coefficients 9.3 MSPS 600 MHz 180 MSPS 180 MHz 300 MSPS 300 MHz
Complex FFT - 1024 point, 16-bit data 10.2 ?s 600 MHz 1 ?s 140 MHz 1 ?s 150 MHz
Using 96 embedded multipliers in the largest
Virtex-II device (XC2V8000)
Using 96 embedded multipliers and 176 Block
Ram in V-II PRO (XC2V125)
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Typical FPGA Design Flow
Plan Budget
HDL RTL Simulation
Create Code/ Schematic
Implement
Functional Simulation
Synthesize to create netlist
Translate
Map
Place Route
Attain Timing Closure
Create Bit File
Timing Simulation
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XILINX Tools for Digital Signal Processing
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MATLAB

• MATLAB, the most popular system design tool, is
  a programming language, interpreter, and modeling
  environment
• Extensive libraries for math functions, signal
  processing, DSP, communications, and much more
• Visualization large array of functions to plot
  and visualize your data and system/design
• Open architecture software model based on base
  system and domain-specific plug-ins

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Simulink

• Simulink - Visual data flow environment for
  modeling and simulation of dynamical systems
• Fully integrated with the MATLAB engine
• Graphical block editor
• Event-driven simulator
• Models parallelism
• Extensive library of parameterizable functions
• Simulink Blockset - math, sinks, sources
• DSP Blockset - filters, transforms, etc.
• Communications Blockset - modulation, etc.

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Traditional Simulink FPGA Flow
System Verification
System Architect
GAP
Simulink
FPGA Designer
HDL
Synthesis
Verify Equivalence
Functional Simulation
Timing Simulation
Implementation
In-Circuit Verification
Download
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XILINX System Generator

• VHDL
• IP
• Testbench
• Constraints File

MATLAB/Simulink
HDL
System Verification
System Generator
Synthesis
Functional Simulation
Implementation
Timing Simulation
Download
In-Circuit Verification
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Handel-C ( http//www.celoxica.com )

• Handel-C is a language for programming
  applications
• Handel-C is not an HDL. It is not C used as an
  HDL
• Handel-C is meaningful to both s/w and h/w
  engineers
• Focus of describing solutions to problems as
  algorithms
• VHDL/Verilog focus on describing the structure of
  a system capable of performing an algorithm.
• Hardware design means controlling space
  (parallelism) and time (sequential processing)
• The par command gives control over space
• The Single clock assignment rule gives control
  over time

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Handel-C Core Language Features

• Standard ISO-C (ANSI-C)
• Control commands if, while, switch etc.
• Functions, structures, pointers
• Extensions for hardware implementation
• par construct - specifies spatial-parallel
  architecture
• Single cycle assignment specifies temporal
  architecture
• Arbitrary widths on variables, expressions etc.
• Type-checked bit-width inference system
• Recursive macro expansion system
• Multiple clock domains with automatic
  metastability resolution
• Powerful bit manipulation operators
• Signals, channels, interfaces to pins, external
  IP cores
• RAMs/ROMs and external pin connections

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• Timing is predictable
• Designer has control over timing
• Simple model assignments take one clock cycle
• Cycle-accurate, fast simulator
• Parallelism is deterministic
• Language extensions include parallel processing
  and communications between parallel elements
• Parallelism based on sound mathematical formalism
• Changes are predictable
• Changes in Handel-C code produce predictable
  changes in hardware
• Enables fast iterative refinement

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Hardware/Software Co-Design

• Enables development of complete systems, ideal
  for
• Board-level prototyping
• Reconfigurable SoC designs
• Hybrid CPU FPGA devices
• Design kit (DK1) facilitates co-design with
• Instruction set simulators
• VHDL simulators
• External C test benches
• Enables hardware/software partitioning decisions
  later in the design cycle
• Rapid conversion of software algorithms into
  custom hardware

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DK1 Design Suite Features
Handel-C

• Compiler Output is
• Optimised
• Deterministic
• Target specific
• Targets Xilinx and Altera net lists directly
  (EDIF)
• RTL VHDL output
• Generation of IP cores (Handel-C, EDIF, VHDL)
• Inclusion of IP cores as black boxes
• GUI for integrated project management, code
  editing and source level debugging
• Fast simulation/debug

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Conclusions

• Exploiting the power of modern FPGAs gets
  increasingly difficult using only traditional
  HDL design methods
• 1 Million Gate XILINX Spartan III costs only 12
  !!!
• New areas of application beyond traditional FPGA
  domains require higher levels of abstraction
• Tools such as Handel-C look promising
• Experience with real designs needed