FPGA Based Network Lock

1
FPGA Based Network Lock

• Amitoj Cheema
• Ajay Bhutani

2
OUTLINE

• Synthesis
• Customization
• Interfacing with ZBT RAM
• Software Issues
• Leon MP

3
Synthesis

• Whole synthesis using Xilinx ISE 6.2 tools
• EDIF2NGD tool doesnt work properly
• Synplify Synthesis doesnt work with ISE 6.2
• XST not recommended by Leon Developers
• Buggy
• Requires different switches for different
  versions
• Hit and Trial
• Cannot synthesize MMU
• Linux cannot work

4
Synthesis Flow
5
Synthesis for ADM-XRC-II

• Requires Delay Interface and a wrapper,
  top_leon
• Required vhdl files, scripts and Makefiles
  available in cheema-xc2v folder on project
  webpage.
• Prepared along the lines of other templates
• Sample bit files included.

6
OUTLINE

• Synthesis
• Customization
• Interfacing with ZBT RAM
• Software Issues
• Leon MP

7
Customization
8
Customization

• GUI Can allow a max of 4 Processors to be
  synthesized at a time.
• More than 4 Processors cannot be synthesized on
  ADM-XRC-2 Board with XC2V3000 Chip. Value can be
  increased by
• Change the value of variable NPROCS in file
  device.vhd
• Change the value of variable masters
  correspondingly in record ahb_config in file
  device.vhd
• Details for how to change the boot code are given
  in the Report.

9
OUTLINE

• Synthesis
• Customization
• Interfacing with ZBT RAM
• Software Issues
• Leon MP

10
Timing Diagram for Read Cycles
Clock
Leon_add
address0
Leon_oen
Lead_out State
Rd_state
r2
r0
r1
r2
Rd_internal
Mem_oen
data0
data
Wait state
11
Timing Diagram for Write Cycles
Clock
Leon_data
data0
Leon_rwen/ Mem_rwen
wr_state
w2
w0
w1
w2
wr_internal
data0
L_data_int
data0
Mem_data
Wait state
12
Delay Interface

• Handles Consecutive reads by Leon processor
• Introduces delay of 1 clock cycle for both read
  and write
• SRAM controller needs to be tweaked to accept 1
  wait state

13
OUTLINE

• Synthesis
• Customization
• Interfacing with ZBT RAM
• Software Issues
• Leon MP

14
Software Issues

• AHB/ APB Address mappings need to be correct in
  drivers
• Wait States
• Correct information needed in BOOT PROM.
• Linux Boot initialization code.
• Debug support Unit Monitor (dsumon).
• Correct Baud rate and Processor Frequency
  Settings in the UART initialization code.

15
Software Issues

• Correct RAM configuration in initialization code
  like
• SRAM /SDRAM present/absent.
• RAM Bank Size.
• Number of RAM banks.(1-4)
• RAM Width.(8-bit,16-bit 32-bit).
• These values are set in MEMCFG2
  register(0x80000004).

16
OUTLINE

• Synthesis
• Customization
• Interfacing with ZBT RAM
• Software Issues
• Leon MP

17
Leon-MP

• Can be configured to have up to 8 Leon procs.
• ADM-XRC II accommodates max. 4
• In house Real Time Operating system RTKER ported
  on the platform.
• Auto-boot on start. Waits for Program on UART 1.

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A 2 Processor Core implementation
PCI
DSU
AHB Controller
User I/O
AMBA AHB
AHB BOOT REG
AHB/APB Bridge
DSL
UART/Timers/IO Ctrl
Memory Controller
AMBA APB
IRQ CTRl1
IRQ CTRl2
19
PSR Register

• Add proc id to PSR to uniquely distinguish a
  processor

PSR
0000
31 17
14 0

Boot Processor with proc id 0
20
Timers Interrupt Controllers

• Each Processor has 2 personal timers.
• Each processor contains its own interrupt
  controller.
• Each processor has two timers each assigned to
  it. The interrupts from these timers are handled
  by the respective interrupt controllers.
• The Boot Processor handles the interrupts from
  UART, network, PCI etc.

21
AHB Boot Slave

• A special slave is provided on the AHB bus with
  the following
• BOOT registers The Boot processor uses these
  registers to provide program start address to the
  application processors.
• Locks Used for Operating System Semaphores.
  Important for data consistency on a multi
  processor platform.

22
BOOT FLOW
23
3 Processor System

• Each processor handles specialized tasks
• 2 processors handle 1 network interface each
• Processor 0 handles encryption/decryption
• Easy measurement of speedup

24
3 Processor System
25
Data Flow
26
Results

• Considerable Speedup
• 225 speedup
• Can be increased further
• Burst accesses
• Pipelining
• Speedup more for more computationally intensive
  algorithms

27
References

• Mailing list (leon_sparc_at_yahoogroups.com)Main
  discussion group for Leon
• Gaisler Research(www.gaisler.com/)
• Official Website for source code and
  documentation
• LEON Toolbox (http//www.leox.org/)Tools for
  development of software on Leon
• Linux SPARC (http//www.ultralinux.org/)Homepage
  of the Linux port to the SPARC architecture..
• Gaisler Linux for LEON (http//www.gaisler.com/pro
  ducts/linux.html)Toolchain, Patches, Simulator,
  Links, etc.

28
References

• AMBA Bus (http//www.arm.com)
• LEON MMU (http//www.ra.informatik.uni-stuttgart.d
  e/LeonMMU/)MMU development for LEON and some
  information on Linux for LEON by Konrad Eisele.
• LEON2 Support for Linux 2.6.x (http//www.ra.infor
  matik.uni-stuttgart.de/holstsn/)Linux 2.6.x
  kernel patches for LEON2 with MMU support.
• The Lion project - Linux for the LEON SPARC
  Processor
• http//wwwhsse.fh-hagenberg.at/Studierende/hse0
  2006/lion/

29
Thanks

• QUESTIONS??