Detailed Placement for Leakage Reduction Using Systematic ThroughPitch Variation

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Detailed Placement for Leakage Reduction Using
Systematic Through-Pitch Variation

• Andrew B. Kahng
• Swamy Muddu
• Puneet Sharma
• CSE and ECE Departments, UC San Diego

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Outline

• Introduction
• Detailed Placement for Leakage Reduction
• Modeling
• Detailed Placement Optimization
• Experimental Setup
• Conclusions

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Introduction

• Leakage and its variability - major concern for
  sub-100nm
• Most significant source of leakage variability
  across-chip linewidth ( gate-length) variation
• In 90nm technology, decrease of linewidth by 10nm
  ? leakage increases by 5X for PMOS and 2.5X for
  NMOS
• Device linewidth control is very challenging from
  lithography and processing standpoints
• ?optical 193nm minimum feature size 60nm (in
  65nm node)
• Resolution Enhancement Techniques E.g., OPC,
  SRAF
• Enable printability of layout features in silicon
• Applied to full-chip layouts after physical
  verification
• RETs are not magic bullets
• SRAF and OPC (and other lithography
  optimizations) guarantee linewidth within
  specific bounds
• Litho non-idealities (such as focus) introduce
  post-litho linewidth variation

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Systematic Linewidth Variation

• RETs (e.g., OPC) compensate for linewidth
  variation at nominal process conditions
• At other process conditions, linewidth varies
  systematically with pitch
• For dense pitches linewidth increases with
  lithography defocus
• For isolated linewidth decreases with defocus
• Linewidth variation with pitch and defocus can be
  obtained by
• Lithography simulation of layout across focus
• Measurements from test chip data
• Variation captured in Bossung lookup tables

Bossung Plot
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How can Placement Improve Leakage?

• Placement dictates the pitches of devices that
  end up in the layout ? specifically those of
  boundary devices
• Consequently, determines printed linewidths
• This work exploit systematic pitch vs. focus
  interactions
• Modify layout pitches to change post-lithography
  linewidths using placement as a knob
• ? exploit litho-dependent variation and optimize
  leakage

Placement affects device pitches
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Outline

• Introduction
• Detailed Placement for Leakage Reduction
• Modeling
• Detailed Placement Optimization
• Experimental Setup
• Conclusions

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Detailed Placement for Leakage

• Detailed Placement refinement step which
  performs small-range perturbations to generate a
  new optimized placement after global placement
• Objective Wirelength and timing
• ? Affects dynamic power
• Detailed placement can affect static power by
  three knobs
• k1 Neighbor selection
• k2 Orientation
• k3 Cell-to-cell spacing
• Our approach
• Step 1 Capture impact of placement on leakage
• Step 2 Utilize leakage information to optimize
  detailed placement using k1, k2 and k3
• Perturb existing placement

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Modeling Placement Impact on Leakage

• Different cell placements result in different
  linewidths
• Capture pitch linewidth interaction in terms of
  leakage
• ? Construct a matrix of leakage cost
• Compute pitch when two cells abut
• Predict linewidth from computed pitch from
  Bossung plot
• Calculate device leakage from linewidths
• Calculate cell leakage from leakage of its devices

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Outline

• Introduction
• Detailed Placement for Leakage Reduction
• Modeling
• Detailed Placement Optimization
• Experimental Setup
• Conclusions

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Single-Row, No-Whitespace Optimization

• Optimization done in small windows (single row)
• Design partitioned into windows, cells in each
  window optimized
• Goal order cells and select the ones to flip to
  minimize leakage cost
• We transform the problem to the famous traveling
  salesman problem
• Node each side of each cell (so, nodes 2
  cells)
• Complete graph with edge weight leakage cost
  matrix entry
• Tour gives ordering and selects cells to be
  flipped
• All nodes ( each side) ordered to minimize cost
  ( sum of leakage cost when two edges touch)
• Additional constraint two edges of the same cell
  must occur consecutively in tour ? we assign -8
  weight
• We use multi-fragment greedy heuristic to solve
  TSP

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Single-Row, No-Whitespace Optimization

• Optimization done in small windows

INVX4
INVX4
NAND2X1
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Multiple Rows, Whitespace Optimization

• Multiple rows
• We exhaustively partition the set of cells into
  rows
• Number of partitions can be extremely large
• Prune number of partitions using row capacity
  constraints
• Best single-row results cached
• Fillers are inserted in whitespaces between cells
• Approach
• Compute number of white spaces (N)
• N FILLx1 cells can be inserted ? Add N vertices
  to TSP
• Merge consecutive fill cells (e.g., 2 FILLx1 ?
  FILLx2)

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Minimizing Wirelength and Timing Impact

• Placement optimization performed on routed
  designs
• Perturbations increase wirelength ? dynamic power
• Smaller window size causes smaller wirelength
  increases
• ? we increase window size progressively in phases
  and accept solution of a phase if it improves
  upon that of last phase
• To minimize timing impact, limit movement of
  timing-critical cells
• Mark critical cells as dont_touch
• All cells connected to nets of critical cells
  also marked as dont_touch to prevent disturabance
  to routing of critical cells
• ECO routing performed with nets of critical cells
  marked as dont_touch

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Outline

• Introduction
• Detailed Placement for Leakage Reduction
• Modeling
• Detailed Placement Optimization
• Experimental Setup
• Conclusions

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Experimental Setup
Bossung LUT Construction
Place Route
Extraction Timing Analysis
Leakage MatrixConstruction
Routed DEF
Optimizer
Fixed cells/nets
ECO Routing
Optimized Design

• Technology 65nm dual-Vth
• Tools RTL Compiler, SoC Encounter, PrimeTime
• Optimizer built on top of OpenAccess API
• Testcases AES (80 util), AES (85 util), DES
  (73 util)

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Results of Placement Optimization
Results for testcase AES (80 utilization)

• identifies results with our measures to
  minimize wirelength and timing bypassed
• As expected, larger windows
• improve leakage, but
• increase wirelength and dynamic power

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Conclusions

• Through-focus linewidth variation with pitch
  contributes to leakage and its variability
• Proposed a novel detailed placement perturbation
  method to minimize leakage from pitch-dependent
  linewidth variation
• Placement perturbation modifies design timing
• Minimize impact by fixing timing-critical cells
• Leakage reduction 5 7 wirelength increase
  7 8
• Not all of wirelength increase translates to
  dynamic power increase and performance
  degradation
• Future work
• Evaluation of the proposed technique for future
  technologies
• Use of detailed placement to improve timing
  robustness