VHDL

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VHDL

• Rabee Shatnawi
• Rami Haddad

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What is this presentation about?!

• This presentation will introduce the key concepts
  in VHDL and the
• important syntax required for most VHDL designs,

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Why to use VHDL?

• In most cases, the decision to use VHDL over
  other languages such as
• Verilog or SystemC, will have less to do with
  designer choice, and more to do with software
  availability and company decisions. Or the
  professor's choice
• -)

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• Verilog has come from a bottom-up tradition and
  has been heavily used by the IC industry for
  cell-based design,
• whereas the VHDL language has been developed
  much more from a topdown perspective.

Of course, these are generalizations and largely
out of date in a modern context
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Entity model interface

• The entity defines how a design element described
  in VHDL connects to other VHDL models
• and also defines the name of the model.
• It allows the definition of any parameters that
  are to be passed into the model using hierarchy.

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Entity definition

• entity test is
• .
• end entity test
• or
• entity test is
• end test

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Ports

• How to connect Entities together?
• -The method of connecting entities together is
  using PORTS.
• PORTS are defined in the entity using the
  following method
• port (
• ...list of port declarations...
• )

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• The port declaration defines the type of
  connection and direction where appropriate.
• port (
• in1, in2 in bit
• out1 out bit
• )

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Entity Port Modes

• in
• signal values are read-only
• out
• signal values are write-only
• buffer
• comparable to out
• signal values may be read, as well
• inout
• bidirectional port

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Generics

• If the model has a parameter, then it is defined
  using generics.
• generic (
• gain integer 4
• time_delay time 10 ns
• )

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Constants

• It is also possible to include model specific
  constants in the entity using the standard
  declaration of constants method
• constant rpullup real 1000.0

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a complete examples, meet our first Entity.
test

• entity test is
• port (
• in1, in2 in bit
• out1 out bit
• )
• generic (
• gain integer 4
• time_delay time 10 ns
• )
• constant rpullup real 1000.0
• end entity test

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Architecture model behavior

• Implementation of the design
• Always connected with a specific entity
• one entity can have several architectures
• entity ports are available as signals within the
  architecture
• Contains concurrent statements

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Basic definition of an architecture

• While the entity describes the interface and
  parameter aspects of the model .
• the architecture defines the behavior.

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• There are several types of VHDL architecture and
  .
• VHDL allows different architectures to be
  defined for the same entity.
• architecture behaviour of test is
• ..architecture declarations
• begin
• ...architecture contents
• end behaviour

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Signals

• Signals are the primary objects describing the
  hardware system and are equivalent to wires.
• They represent communication channels among
  concurrent statements of system application.
• Signals can be declared in
• Package declaration
• Architecture
• Block
• Subprograms

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Hierarchical design

• Functions
• Packages
• Components
• Procedures

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Functions

• A simple way of encapsulating behavior in a model
  that can be reused in multiple architectures.
• Can be defined locally to an architecture or more
  commonly in a package

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• The simple form of a function is to define a
  header with the input and output variables as
  shown below
• function name (input declarations) return
  output_type is
• ... variable declarations
• begin
• ... function body
• end

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• function mult (a,b integer) return integer is
• begin
• return a b
• end

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Package Function containers

• package name is
• ...package header contents
• end package
• package body name is
• ... package body contents
• end package body

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Component
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• library ieee
• use ieee.std_logic_1164.all
• -- here is the entity
• entity halfadd is
• port (a, b in std_logic
• sum, c out std_logic)
• end halfadd
• architecture comp of halfadd is
• begin
• -- a concurrent statement implementing the and
  gate
• c lt a and b
• -- a concurrent statement implementing the xor
  gate
• sum lt a xor b
• end comp

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• library ieee
• use ieee.std_logic_1164.all
• entity fulladd is
• port (ina, inb, inc in std_logic
• sumout, outc out std_logic)
• end fulladd
• architecture top of fulladd is
• component halfadd
• port (a, b in std_logic
• sum, c out std_logic)
• end component
• signal s1, s2, s3 std_logic
• begin
• -- a structural instantiation of two half adders
• h1 halfadd port map( a gt ina, b gt inb,
• sum gt s1, c gt s3)
• h2 halfadd port map( a gt s1, b gt inc,
• sum gt sumout, c gt s2)
• outc lt s2 or s3

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VHDL

• Case insensitive
• Comments '--' until end of line Statements are
  terminated by ''(may span multiple lines)
• List delimiter ','
• Signal assignment 'lt
• User defined names
• letters, numbers, underscores
• start with a letter

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VHDL . Identifier

• (Normal) Identifier Letters, numerals,
  underscores
• Case insensitive
• No two consecutive underscores
• Must begin with a letter
• Not a VHDL keyword

mySignal_23      -- normal identifierrdy, RDY,
Rdy    -- identical identifiersvector__vector  -
-  X special characterlast of Zout     --  X
white spacesidle__state      --  X consecutive
underscores24th_signal      --  X begins with
a numeralopen, register   --  X VHDL keywords
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VHDL Structural Elements

• Entity Interface Architecture
• Implementation, behavior, function
• Configuration Model chaining, structure,
  hierarchy
• Process Concurrency, event controlled
• Package Modular design, standard solution,
• data types, constants
• Library Compilation, object code

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Hierarchical Model Layout

• VHDL allows for a hierarchical model layout,
  which means that a module can be assembled out of
  several submodules. The connections between these
  submodules are defined within the architecture of
  a top module. As you can see, a fulladder can be
  built with the help of two halfadders (module1,
  module2) and an OR gate (module3).

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Component example
ENTITY half_adder IS PORT ( A, B
IN STD_LOGIC sum, carry OUT
STD_LOGIC ) END half_adder
ARCHITECTURE structural OF half_adder IS
COMPONENT xor2

PORT ( a, b IN STD_LOGIC c
OUT STD_LOGIC ) END COMPONENT COMPONENT
and2 PORT ( a, b
IN STD_LOGIC c OUT STD_LOGIC
) END COMPONENT BEGIN
ex1 xor2 PORT MAP ( a gt a, b gt
b, c gt sum ) or1 and2 PORT MAP ( a gt a, b
gt b, c gt carry )
END structural
begin     MODULE1 HALFADDER     port map(
A, B, W_SUM, W_CARRY1 )     MODULE2 HALFADDER
     port map ( W_SUM, CARRY_IN,                 
     SUM, W_CARRY2 )     MODULE3 ORGATE    
port map ( W_CARRY2, W_CARRY1, CARRY
) end STRUCT
entity FULLADDER is   port (A,B, CARRY_IN in   b
it           SUM, CARRY     out bit)end FULLA
DDERarchitecture STRUCT of FULLADDER is   signa
l W_SUM, W_CARRY1, W_CARRY2  bit    component
 HALFADDER      port (A, B                 in   
bit              SUM, CARRY  out bit)   
end component    component  ORGATE      port (A
, B  in   bit              RES  out bit)   
end componentbegin
begin    MODULE1 HALFADDER                    
 port map (  A           gt A,                   
                  SUM     gt W_SUM,              
                        B           gt B,        
                             CARRY gt W_CARRY1
)   . . .end STRUCT
ENTITY and2 IS PORT ( a, b
IN STD_LOGIC output OUT
STD_LOGIC ) END and2
ARCHITECTURE gate OF and2 IS BEGIN
output lt ( a AND b
) AFTER 5ns END gate
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Process

• The process in VHDL is the mechanism by which
  sequential statements can be executed in the
  correct sequence, and with more than one process,
  concurrently.
• Contains sequentially executed statements
• Exist within an architecture,
• only Several processes run concurrently
• Execution is controlled either via sensitivity
  list (contains trigger signals), or
  wait-statements

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Process
JustToShow process Begin Some statement
1 Some statement 2 Some statement 3 Some
statement 4 Some statement 5 end process
JustToShow

• JustToShow process
• Begin
• Some statement 1
• Some statement 2
• Some statement 3
• Some statement 4
• waitltconditiongt
• end process JustToShow

• Wait for type expression
• Wait until condition
• Wait on sensitivity list
• Complex wait

Wait for 10ns
Wait until CLK1
Wait on Enable
Wait unit date after 10ns
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Process

• JustToShow process ( )
  
• Begin
• Some statement 1
• Some statement 2
• Some statement 3
• Some statement 4
• end process JustToShow

• VHDL provides a construct called sensenitivity
  list of a process
• The list specified next to the process keyword.
• The same as wait on sensitivity_list at the end
  of a process

JustToShow process
Begin Some statement 1 Some statement
2 Some statement 3 Some statement 4 wait
on end process JustToShow
SomeSig
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Process

• JustToShow process (signa1,signal2,signal3)
  
• Begin
• Some statement 1
• Some statement 2
• Some statement 3
• Some statement 4
• Some statement 5
• end process JustToShow

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Example
Signa1 0 Signal35
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Example

• process(C,D)
• begin
• Alt2
• BltAC
• AltD1
• EltA2
• end process

Alt2
AltD1

• A1
• B1
• C1
• D1
• E1

3
2
BltAC
EltA2
2
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Variables

• Variables are available within processes
• Named within process declarations
• Known only in this process
• Immediate assignment
• An assignment to a variable is made with
  symbol.
• The assignment take instance effect and each
  variable can be assigned new values as many times
  as needed.
• A variable declaration look similar to a signal
  declaration and starts with variable keyword
• Keep the last value
• Possible assignments
• Signal to variable
• Variable to signal
• Types have to match

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Variables vs. Signals

• Signals
• In a process, only the last signal assignment is
  carried out
• Assigned when the process execution is suspended
• lt to indicate signal assignment
• Variables
• Assigned immediately
• The last value is kept
• to indicate variable assignment

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Variables vs. Signals (contd.)
A
C

X

X
B
B
C
C

Y

Y
B
B
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Variables

• process(C,D)
• Variable Av,Bv,Ev integer 0
• begin
• Alt2
• BvltAvC
• AvltD1
• Ev lt Av2
• A ltAv
• B ltBv
• E ltEv
• end process

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The world is not sequential

• Its convention to specify things in a sequential
  way, this is not the simplest way to describe
  reality.
• Processes are concurrent statements
• Several processes run parallel linked by signals
  in the sensitivity list
• sequential execution of statements
• Link to processes of other entity/architecture
  pairs via entity interface

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• Architecture SomeArch of SomeEnt is
• Begin
• P1process(A,B,E)
• Begin
• Somestatment
• Somestatment
• Somestatment
• DltSomeexpression
• End process P1

P2process(A,C) Begin Somestatment Somestatment
Somestatment End process P1
P3process(B,D) Begin Somestatment Somestatment
Somestatment End process P1
end Architecture SomeArch
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IF Statement
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Case statement
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For loop

• entity FOR_LOOP is   port (A  in    integer rang
  e 0 to 3           Z   out bit_vector (3 downto
   0)) end FOR_LOOP  architecture EXAMPLE of FO
  R_LOOP isbegin      process (A)   begin      Z
   lt "0000"       for  I  in  0 to 3 
  loop         if (A  I) then            Z(I) lt 
  1         end if       end loop
          end processend EXAMPLE

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Exit Next

• The exit command allows a FOR loop to be exited
  completely. This can be useful when a condition
  is reached and the remainder of the loop is no
  longer required. The syntax for the exit command
  is shown below
• for i in 0 to 7 loop
• if ( i 4 ) then
• exit
• endif
• endloop
• The next command allows a FOR loop iteration to
  be exited, this is slightly different to the exit
  command in that the current iteration is exited,
  but the overall loop continues onto the next
  iteration. This can be useful when a condition is
  reached and the remainder of the iteration is no
  longer required. An example for the next command
  is shown below
• for i in 0 to 7 loop
• if ( i 4 ) then
• next
• endif
• endloop

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Conditional Signal Assignment

• entity CONDITIONAL_ASSIGNMENT is   port (A, B, C,
   X  in   bit_vector (3 downto 0)            Z_C
  ONC  out bit_vector (3 downto 0)            Z_S
  EQ     out bit_vector (3 downto 0))end
  CONDITIONAL_ASSIGNMENTarchitecture EXAMPLE of CO
  NDITIONAL_ASSIGNMENT isbegin   -- Concurrent
  version of conditional signal assignment   Z_CONC
  lt B when X  "1111" else                       
   C when X gt "1000" else                        A
     -- Equivalent sequential statements   process
  (A, B, C, X)   begin       if  (X  "1111") 
  then         Z_SEQ lt B       elsif
   (X gt "1000")  then         Z_SEQ lt C      els
  e         Z_SEQ lt A       end if   end
  processend EXAMPLE

• TARGET lt VALUETARGET lt VALUE_1 when
  CONDITION_1 else                    VALUE_2 when
  CONDITION_2 else                    . .
  .                    VALUE_n

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Selected Signal Assignment

• entity SELECTED_ASSIGNMENT is   port (A, B, C, X 
   in   integer range 0 to 15            Z_CONC 
   out integer range 0 to 15            Z_SEQ    
  out integer range 0 to 15)end SELECTED_ASSIGNME
  NT architecture EXAMPLE of SELECTED_ASSIGNMENT i
  sbegin
•    -- Concurrent version of selected signal
  assignment   with X select      Z_CONC lt A
  when 0,                           B when 7
  9,                           C when 1 to
  5,                           0 when
  others   -- Equivalent sequential
  statements   process (A, B, C,
  X)   begin      case X is         when 0
          gt Z_SEQ lt A         when 7 9    gt
  Z_SEQ lt B         when 1 to 5  gt Z_SEQ lt
  C         when others gt Z_SEQ lt 0   end
  processend EXAMPLE

with EXPRESSION select  TARGET lt VALUE_1 when
CHOICE_1,                       VALUE_2 when
CHOICE_2 CHOICE_3,                       VALUE_
3 when CHOICE_4 to CHOICE_5,                     
                          VALUE_n when
others
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Operators
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Subprograms

• Functions
• function name can be an operator
• arbitrary number of input parameters
• exactly one return value
• no WAIT statement allowed
• function call ltgt VHDL expression
• Procedures
• arbitrary number of parameters of any possible
  direction (input/output/inout)
• RETURN statement optional (no return value!)
• procedure call ltgt VHDL statement
• Subprograms can be overloaded
• Parameters can be constants, signals, variables
  or files

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function

• architecture EXAMPLE of FUNCTIONS
  is function COUNT_ZEROS (A bit_vector)
  return integer is      variable ZEROS
  integer   begin      ZEROS 0      for I
  in A'range loop         if A(I) '0'
  then            ZEROS ZEROS 1         end
  if      end loop      return ZEROS   end
  COUNT_ZEROS   signal WORD     bit_vector(15
   downto 0)   signal WORD_0 integer   signal
  IS_0         boolean

begin   WORD_0 lt COUNT_ZEROS(WORD)   pro
cess   begin      IS_0 lt true      if
COUNT_ZEROS("01101001") gt 0 then         IS_0 lt
false      end if      wait   end
processend EXAMPLE
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procedure

• architecture EXAMPLE of PROCEDURES
  is   procedure COUNT_ZEROS                      
                (A in bit_vectorsignal Q out
  integer) is      variable ZEROS
  integer   begin      ZEROS 0      for I
  in A'range loop         if A(I) '0'
  then            ZEROS ZEROS 1         end
  if      end loop      Q lt ZEROS
•    end COUNT_ZEROS  signal COUNT
  integer   signal IS_0      booleanbegin   pr
  ocess   begin      IS_0 lt true      COUNT_ZER
  OS("01101001", COUNT)      wait for 0
  ns      if COUNT gt 0 then         IS_0 lt
  false      end if      wait   end
  processend EXAMPLE

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Data Types

• Each object in VHDL has to be of some type, which
  defines possible values and operations that can
  be performed on this object (and other object of
  the same type) .
• VHDL is strongly typed language which causes that
  two types defined in exactly the same way but
  differing only by names will be considered
  differently.
• If a translation from one type to another is
  required, then type convention must be applied
  even if the two types are similar.

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Data Types
A physical type is a numeric type for
representing some physical quantity, such as
mass, length, time or voltage. type distance is
range 0 to 1E5 units um mm 1000 um In_a25400
um end units Variable Dis1,dis2
Distance Dis128mm
An integer type is a scalar whose set of values
include integer numbers in specific
range. type byte_int is range 0 to 255 type
voltage_level is range 0 to 5
An enumeration type is a type whose values are
defined by listing (enumerating) them
explicitly. type logic_level is (unknown, low,
undriven, high)
A floating point type is a discrete approximation
to the set of real numbers in a specified
range. type signal_level is range 10.00 to
10.00
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Data Types
A record type allows declaring composite objects
whose elements can be from different types. Type
RegName is (AX,BX,DX) Type Operation is record
Mnemonicstring (1 to 10) OpCodeBit_Vector(3
downto 0) Op1,op2,RegRegName End
record Variable Instr3 Operation Instr3.
Mnemonic Mul AX, BX Inst3.Op1Ax

• Is an indexed collection of elements all of the
  same type. Arrays may be one-dimensional (with
  one index) or multidimensional (with a number of
  indices).
• type VAR is array (0 to 7) of integer
• constant SETTING VAR (2,4,6,8,10,12,14,16)
  
• type VECTOR2 is array (natural range ltgt,
  natural range ltgt) of std_logic
• variable ARRAY3x2 VECTOR2 (1 to 3, 1 to 2))
  ((1,0), (0,-), (1, Z))

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Subtype

• A type with a constraints. A value belong to a
  subtype of a given type if it belongs to the type
  and satisfied the constraints.
• Subtype Digits is Integer range 0 to 9
• Integer is a predefined type and the subtype
  digits will constraints the type to ten values
  only.

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Standard Data Types
package STANDARD is   type BOOLEAN is (FALSE,TRUE
)   type BIT is (0,1)   type CHARACTER is 
(-- ascii set)   type INTEGER is range         
                      -- implementation_defined  
 type REAL is range                              
--  implementation_defined   -- BIT_VECTOR, STRIN
G, TIMEend STANDARD

• Every type has a number of possible values
• Standard types are defined by the language
• User can define his own types

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Alias

• Signal Instruction Bit_vector(15 downto 0)
• Alias OpCode Bit_vector(3 downto 0) is
  Instruction(15 downto 12)
• Alias Source Bit_vector(1 downto 0) is
  Instruction(11 downto 10)
• Alias design Bit_vector(1 downto 0) is
  Instruction(9 downto 8)
• Alias Immdata Bit_vector(7 downto 0) is
  Instruction(7 downto 0)

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Aggregate

• A basic operation that combines one or more
  values into a composite value of a record or
  array type
• Variable data_1 Bit_vecot(0 to 3)
  (0,1,0,1)
• Variable data_1 Bit_vecot(0 to 3)
  (1gt1,0gt0, 3gt1,2gt0)
• Signal data_Bus std_logic_vector (15 downto 0)
• data_Buslt(15 downto 8 gt 0, 7 downto 0
  gt1)
• Signal data_Bus std_logic_vector (15 downto 0)
• data_Buslt(14downto 8 gt 0, othersgt1)
• Signal data_Bus std_logic_vector (15 downto 0)
• data_Buslt(othersgtz)
• Type Status_record is record
• CodeInteger
• Namestring(1 to 4)
• End record
• Variable Status_var Status_record
  (codegt57, namegtMOVE)

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Concatenation

• architecture EXAMPLE_1 of CONCATENATION
  is   signal BYTE                  bit_vector (7
  downto 0)   signal A_BUS, B_BUS bit_vector (3
  downto 0)begin   BYTE   lt A_BUS B_BUSend
  EXAMPLE
• Variable Bytedat bit_vector(7 downto 0)
• Alias Modulus bit_vector(6 downto 0) is
  bytedat(6 downto 0)
• Bytedate1 modulas

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Attribute

• Attributes are a feature of VHDL that allow you
  to extract additional information about an object
  (such as a signal, variable or type) that may not
  be directly related to the value that the object
  carries.
• Type table is array (1 to 8) of Bit
• Variable array_1 table00001111
• Arrat_1left, the leftmost value of table array
  is equal to 1
• architecture example of enums is
•     type state_type is (Init, Hold, Strobe, Read,
  Idle)
•     signal L, R state_type
• begin
•     L lt state_typeleft  -- L has the value of
  Init
•     R lt state_typeright  -- R has the value of
  Idle
• end example
• (clock'EVENT and clock'1')
• type state_type is (Init, Hold, Strobe, Read,
  Idle)
•     variable P integer state_typepos(Read)
  -- P has the value of 3
•  type state_type is (Init, Hold, Strobe, Read,
  Idle)
•    variable V state_type state_typeval(2)
  -- V has the value of Strobe

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Reference

• http//www.seas.upenn.edu/ese201/vhdl/vhdl_primer
  .html_Toc526061356
• http//www.vhdl-online.de/vhdl/tutorial/
• http//tams-www.informatik.unihamburg .de
  /vhdl/doc/cookbook/VHDL Cookbook .pdf