SODA:%20A%20Low-power%20Architecture%20For%20Software%20Radio

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SODA A Low-power Architecture For Software Radio

• Yuan Lin1, Hyunseok Lee1, Mark Woh1, Yoav Harel1,
  
• Scott Mahlke1, Trevor Mudge1, Chaitali
  Chakrabarti2, Krisztian Flautner3
• 1Advanced Computer Architecture Lab, University
  of Michigan
• 2Department of Electrical Engineering, Arizona
  State University
• 3ARM, Ltd.

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Anatomy of 3G Cellular Phone
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Advantages of Software Defined Radio

• Multi-mode operations
• Lower costs
• Faster time to market
• Prototyping and bug fixes
• Chip volumes
• Longevity of platforms
• Protocol complexity favors software dominated
  solutions
• Enables future wireless communication innovations
• Cognitive radio

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Why is SDR Challenging?

• SDR Design Objectives for 3G and WiFi
• Throughput requirements
• 40Gops peak throughput
• Power budget
• 100mW500mW peak power

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The Anatomy of Wireless Protocols
1. Filtering suppress signals outside frequency
band
2. Modulation map source information onto signal
waveforms
3. Channel Estimation Estimate channel condition
for transceivers
4. Error Correction correct errors induced by
noisy channel
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SDR Application Specific Design

• Wireless protocols are systems of DSP algorithms
• System-level
• Example Specification of W-CDMA DCH channel
• Algorithm-level
• Example Implementation of a 64 point FFT

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System Level Design Decisions
System Characteristics SODA Architectural Decisions
1. Algorithm macro-pipelining with streaming computation 1. Multi-core system 2. Communication through DMA
2. Multiple periodic real-time deadlines 3. Deterministic hardware behavior 4. Compile-time algorithm mapping and scheduling
3. Low streaming throughput between algorithms 5. Low throughput interconnect
4. Heterogeneous inter- algorithm communication 6. Multi-level scratchpad memories
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SODA System Architecture

• 4 PEs
• static kernel mapping and scheduling
• SIMDScalar units
• 1 ARM GPP controller
• scalar algorithms and protocol controls

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SODA Memory Organization

• 2-Level scratchpad memories
• 12KB Local scratchpad memory for stream queues
• 64KB global scratchpad memory for large buffers
• Low-throughput shared bus
• 200MHz 32-bit bus
• inter-PE communication using DMA

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DSP Algorithm Characteristics

• 8 to 16-bit precision
• Vector operations
• long vectors
• constant vector size
• Static data movement patterns
• Scalar operations

Algorithms Type of Computation Vector Width
W-CDMA W-CDMA W-CDMA
Filter Vector 64
Modulation Vector 2560
Channel Est. Vector 320
Error Correction Mixed 8 or 256
802.11a 802.11a 802.11a
Filter Vector 33
Modulation (FFT) Vector 64
Channel Est. Mixed 16
Error Correction Mixed 64
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SODA PE Architecture
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SODA PE SIMD Pipeline
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SODA PE SIMD Pipeline
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SODA PE SIMD Shuffle Network
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SODA PE Scalar Pipeline
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W-CDMA Mapping On SODA
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SDR Performance Distribution

• 802.11a has higher number of total computational
  cycles
• W-CDMA requires higher computational cycles per
  bit

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Power Consumption at 180nm

• Wide SIMD requires higher number of pipeline
  registers
• 802.11a consumes higher power than W-CDMA
• 8-bit W-CDMA computation versus 16-bit 802.11a
  computation

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Summary
SDR Hardware Requirements SODA Results
Comp. requirements 10 100 GOPS W-CDMA 802.11a 1.3 2 GOPS (with SODA LIW ops)
Sub-watt power budget 0.2 Watt for cellular phones 180nm 3 Watts (area 26.6mm2) 90nm (est.) 0.5 Watt (6.7 mm2)

• Key features of SODA
• Multi-PE with scratchpad memories
• Low throughput shared bus
• 2-issue LIW SIMD(Scalar or AGU)
• 32-wide SIMD processing
• SIMD shuffle network

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Conclusion Future Work

• Conclusion
• 2G and 3G SDR solutions are achievable in 90nm
• Optimization opportunities at the algorithm,
  software and hardware levels
• Future Work
• SDR for Idle mode operation (ISLPED 06)
• SODA for 4G protocols
• Application-specific language for SDR
• Compiler for SODA

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Questions?

• www.eecs.umich.edu/sdrg

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Backup Slides
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Different Levels of Software Radio
Tier Name Description
Tier 0 Hardware Radio (HR) Implemented using hardware components. Cannot be modified
Tier 1 Software Controlled Radio (SCR) Only control functions are implemented in software inter-connects, power levels, etc.
Tier 2 Software Defined Radio (SDR) Software control of a variety of modulation techniques, wide-band or narrow-band operation, security functions, etc.
Tier 3 Ideal Software Radio (ISR) Programmability extends to the entire system with analog conversion only at the antenna.
Tier 4 Ultimate Software Radio (USR) Defined for comparison purposes only
ltsourcehttp//www.sdrforum.orggt
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Power Methodology

• Our flow sequence was
• Design Compiler and Silicon Ensemble
• For Initial Floorplan Estimation
• Physical Compiler
• For placement and Optimization
• Silicon Ensemble
• Routing
• We optimized for power and delay
• Blocks like memory were generated with Artisan
  Memory Generators
• We used the Synopsys IP Blocks as much as
  possible to get better compiled blocks

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