Low-Power High-Level Synthesis Techniques

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Low-Power High-LevelSynthesis Techniques

• Presented By Mohsen Yousefpour
• Professor Dr. S. Mahdi Fakhraei
• ASIC Course Seminar
• University Of Tehran,
• School of Electrical and Computer Engineering
• Spring 2006

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Outline

• Power Problem In DSM Technologies
• Post Processing Techniques For Power Consumption
  Control
• Synthesis Techniques For Power Consumption
  Control
• Interconnect-Aware Synthesis
• References

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Power Problem In DSM Technologies

• There are two major sources of power in a CMOS
  circuit, dynamic power and static power
• With the shrinking of feature size and lowering
  of VDD, static power has become as important as
  dynamic power
• In a circuit, in DSM technologies, a data
  transfer wire between datapath units can be
  hundreds of ? long, which is equivalent to tens
  of gates in terms of input capacitance. Its power
  consumption is thus nonnegligible

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Power Problem In DSM Technologies

• Taking into account physical design information
  and coupling capacitance to estimate power
  consumption accurately is necessary
• There are two major category to control power
  consumption
• Post processing techniques
• Synthesis techniques

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Post Processing TechniquesFor Power Consumption
Control

• Signal Gating
• It is well known that there can be significant
  spurious switching activity (SSA), i.e. activity
  not required by behavioral specification, in
  datapath units. SSA consumes a significant
  percentage of total power consumption
• Signal gating-based (also known as operand
  isolation) power management has been used to
  freeze the inputs to a DPU to suppress SSA

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Post Processing TechniquesFor Power Consumption
Control

• Signal Gating Techniques
• Signal Gating With Filler Values
• If one part of a circuit is not doing anything
  useful in a given cycle, ideally its inputs
  should be frozen to a statistically chosen value,
  which we call it filler value.
• The overhead for setting an input to a fixed
  value is very low compared to the overhead for
  latches
• Tri-state Buffer Based Technique
• In cases which the consecutive idle cycles are
  not long enough, instead of using a filler value,
  we can use tri-state gating without letting its
  output voltage value drift to cause any problem

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Post Processing TechniquesFor Power Consumption
Control

• Signal Gating Techniques
• Clock Gating
• Provides a way to selectively stop the clock, and
  thus force the original circuit to make no
  transition, whenever the computation that is to
  be carried out at the next clock cycle is
  redundant.

Clock gating logic for ALU in a typical processor
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Post Processing TechniquesFor Power Consumption
Control

• Signal Gating Techniques
• Guarded Evaluation
• The approach is based on placing some guard
  logic, consisting of transparent latches with an
  enable signal, at the inputs of each block of the
  circuit that needs to be power-managed.

Example of guard logic insertion 3
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Post Processing TechniquesFor Power Consumption
Control

• Bus Encoding For Low Power
• Power on buses can be reduced by properly coding
  the data and/or address bus values so as to
  minimize the number of transitions that occur on
  the bus.
• Bus coding has been proposed to reduce switching
  activity
• Bus Encoding Techniques
• Working Zone Method
• Bus Invert
• T0
• etc

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Synthesis TechniquesFor Power Consumption Control

• High Level Synthesis Tool takes as its input a
  behavioral description in the form of a
  control-data flow graph (CDFG)
• It outputs a power-optimized register-transfer
  level circuit
• New synthesis tools for DSM technologies, not
  only reduce datapath unit power consumption in
  the resultant RTL architecture, but also
  optimizes interconnects for power

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Synthesis TechniquesFor Power Consumption Control

• High-Level Synthesis techniques
• Multiple Supply Voltage and Threshold Voltage
  Design
• Using different voltages in different parts of a
  chip may reduce the global energy consumption of
  a design at a rather small cost in terms of
  algorithmic and/or architectural modifications.
• Clock Frequency is autonomously and dynamically
  controlled while supply voltage is adaptively
  controlled resulting in the leakage power
  compensation effect
• Nodes with the maximum slack are assigned to
  lower voltages in such a way that timing
  constraints are not violated. The algorithm stops
  when no positive slack exists in the data flow
  graph.
• Using parameterized function unit library that
  provides parameters such as VDD, VTH, the
  capacity CL, and etc of each function unit. The
  output is the scheduled DFG with the minimum or
  near minimum power consumption under given
  constraints.

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Synthesis TechniquesFor Power Consumption Control

• High-Level Synthesis techniques
• Multiple Supply Voltage and Threshold Voltage
  Design

Example of multiple supply voltage design 3
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Synthesis TechniquesFor Power Consumption Control

• High-Level Synthesis techniques
• Computational Kernels
• Synthesizing a circuit that is fast and
  power-efficient under typical input stimuli, but
  continues to operate correctly even when uncommon
  input stimuli are applied to the circuit.
• State Machine Decomposition
• The basic idea is to decompose the STG of a
  finite-state machine (FSM) into two STGs that
  jointly produce the equivalent inputoutput
  behavior as the original machine. Power is saved
  because, except for transitions between the two
  sub-FSMs, only one of the sub-FSMs needs to be
  clocked.

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Synthesis TechniquesFor Power Consumption Control

• High-Level Synthesis techniques
• State Assignment
• State encoding/assignment, as a crucial step in
  the synthesis of the controller circuitry
• Retiming
• This technique changes the location of registers
  in the design in order to achieve one of the
  following goals
• minimize the clock period
• minimize the number of registers
• minimize the number of registers for a target
  clock period.
• The reason for power savings is that in this case
  the output of a register switches only at the
  arrival of the clock signal as opposed to
  potentially switching many times in the clock
  period.

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Synthesis TechniquesFor Power Consumption Control

• Interconnect-Aware Synthesis
• Evaluating the power consumption in the steering
  logic and clock distribution network as well as
  data transfer wires, using early floorplanning
  information.
• Coupling capacitances are expected to dominate
  the wire capacitance in future technologies, so
  synthesis tool should take coupling into account
  while estimating wire power consumption.
• Creating locality in the physical implementation

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Interconnect-Aware Synthesis

• RTL Interconnect power estimation
• Data Transfer Wires
• Local Power Model
• In DSM technologies, the switched capacitance of
  a wire depends on its neighbors switching
  activity, which determines how the coupling
  capacitances between wires are charged and
  discharged
• Three Line Switching Pattern the unit-length
  switched capacitance of a wire can be found by
  observing the switching patterns on the wire and
  its two immediate neighbors.
• Pattern-Power Table For each metal layer, we
  need to generate a different pattern-power table.

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Interconnect-Aware Synthesis

• RTL Interconnect power estimation
• Data Transfer Wires
• Global Power Model
• A data transfer between two DPUs is assumed to be
  center-to-center and rectilinear for simplicity.
• it is shown that more than 95 of wires in an
  application-specific integrated circuit (ASIC)
  are routed in a Manhattan fashion
• Different Output Network Topologies

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Interconnect-Aware Synthesis

• RTL Interconnect power estimation
• Data Transfer Wires
• Output Network Topologies

Different topologies of an output network (a)
fully dedicated, and trunk-branches output
network with the trunk being (b) horizontal and
(c) vertical. 1
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Interconnect-Aware Synthesis

• RTL Interconnect power estimation
• Data Transfer Wires
• Output Network Topologies

Different output network topologies for (a) one
DPU sending data to two others (b) MST, (c)
fully dedicated, and (d) trunk-branches. 1
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Interconnect-Aware Synthesis

• RTL Interconnect power estimation
• Data Transfer Wires
• Output Network Topologies
• Since can be either larger or smaller than , none
  of these topologies is always better than the
  others in terms of power consumption.

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Interconnect-Aware Synthesis
Local and global wire models, behavior profiler,
and RTL floorplanner used to estimate data
transfer wire power consumption. 1
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Interconnect-Aware Synthesis

• RTL Interconnect power estimation
• Data Transfer Wires
• Steering Logic
• The power consumption is based on their RTL power
  macro model
• Clock Distribution Network
• After floorplanning, an MST is constructed for
  these clocked units. The power consumption of the
  MST is estimated using unit-length switched
  capacitance and the total length of the MST.
• Buffers
• The total switched capacitance of inserted
  buffers is about 1.1 times the total switched
  capacitance of the corresponding wire and
  synthesis tool treat them as an integral part of
  the wire.

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Interconnect-Aware Synthesis

• Interconnect-Aware Binding
• Neighborhood-Sensitive Binding
• The data communication cost will be reduced if
  DPUs, which exchange data, are placed close to
  each other in the floorplan.
• Neighborhood Crowd Parameter (With threshold
  value 4)
• Using two binding moves (Sharing and Splitting)
  to optimize NC
• Communication-Sensitive Binding
• This tends to merge DPUs, which have intensive
  data-exchange between them.

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Interconnect-Aware Synthesis
Framework of the interconnect-aware high-level
synthesis tool for low power. 1
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Interconnect-Aware Synthesis
Another Example, Flow of the heuristic iterative
improvement algorithm 2
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References

1. Lin Zhong Et Al, Interconnect-aware Low-power
   High-level Synthesis, IEEE Transactions On
   Computer-aided Design Of Integrated Circuits And
   Systems, Vol. 24, No. 3, March 2005
2. Jianfeng Huang Et Al, A Fast Algorithm For Power
   Optimization Using Multiple Voltages In Data Path
   Synthesis, 2005 6th International Conference On
   ASIC Proceedings, ASICON05, Shanghai,
   2005.10.17-20, 902-905
3. M. Pedram, A. Abdollahi, Low-power Rt-level
   Synthesis Techniques A Tutorial, IEE
   Proc.-Comput. Digit. Tech., Vol. 152, No. 3, May
   2005
4. Masakatsu Nakai Et Al, Dynamic Voltage And
   Frequency Management For Alow-power Embedded
   Microprocessor, IEEE Journal Of Solid-state
   Circuits, Vol. 40, No. 1, January 2005
5. Achim Rettberg et al, A new Design Partitioning
   Approach for Low Power High-Level Synthesis,
   Proceedings of the Third IEEE International
   Workshop on Electronic Design, Test and
   Applications (DELTA06)
6. Deniz Dal et al, Power Islands A High-Level
   Synthesis Technique for Reducing Spurious
   Switching Activity and Leakage, IEEE
   International Midwest Symposium on Circuits and
   Systems (MWSCAS'05), Cincinnati, Ohio, August
   2005.

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Questions

• ?