Binary-Decision-Diagram (BDD) Application on Pass-Transistor Logic Design Tao Lin School of EECS, Ohio University March 12, 1998

1
Binary-Decision-Diagram (BDD) Application on
Pass-Transistor Logic DesignTao LinSchool of
EECS, Ohio UniversityMarch 12, 1998
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Content

• How to build the BDD for a certain function
• Properties of BDD
• Manipulation of BDD
• Application of BDD to the Pass-Transistor design.

3
Build a BDD for F
F
Fabcbdcd
FaFaaFa
4
Build a BDD for F
F
Fabcbdcd
a
E
T
FaFaaFa
b
b
Fa(bFabbFab) a(bFabbFab)
T
E
T
E
ccd
d
cd
d
5
Build a BDD for F
Order altbltcltd
F
Fabcbdcd
a
T
E
FaFaaFa
b
b
Fa(bFabbFab) a(bFabbFab)
T
E
T
E
c
c
E
E
. . .
E
T
d
T
T
1
0
6
Re-ordered-BDD (optimal)
Fabcbdcd
Order bltcltaltd
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Properties of BDD

• The Reduced Ordered BDD (ROBDD) is a canonical
  form
• The size of the BDD (the number of nodes is
  exponential in the number of variables in the
  worst case however, BDDs are well-behaved for
  many functions that are not amenable to two-level
  representations (e.g., XOR)

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Properties of BDD

• The logical AND and OR of BDDs have the same
  complexity. Complementation is inexpensive
• Tautology can be solved in constant time. Indeed,
  F is a tautology if and only if its BDD consists
  of the terminal node 1

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Properties of BDD

• Covering problems can be solved in time linear in
  the size of the BDD representing the constrains

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On the other hand

• BDD sizes depend on the ordering. Finding a good
  ordering is not always simple
• There are functions for which the SOP of POS
  representations are more compact than BDD

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On the other hand

• In some cases SOP/POS forms are closer to the
  final implementation of a circuit. For instance,
  if we want to implement a PLA.

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Manipulation of BDD
a
a
a
T
E
1
0
13
Manipulation of BDD
a
a
a
T
E
1
0
14
Manipulation of BDD
a
a
a
T
E
1
0
15
Manipulation of BDD
a
a
a
T
E
1
0
16
Minimization of BDD

• Identification of isomorphic sub-graphs
• Removal of redundant nodes.

17
Minimization of BDD
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Minimization of BDD
F
b
T
E
c
c
E
T
E
T
d
d
d
d
T
E
T
T
T
E
E
E
a
a
1
0
1
0
1
0
E
T
E
T
1
0
1
0
Fabcbdcd
19
Minimization of BDD
F
b
T
E
c
c
E
T
d
d
T
E
T
E
a
a
1
0
E
T
E
T
1
0
1
0
Fabcbdcd
20
Minimization of BDD
F
b
T
E
c
c
T
E
d
d
T
E
T
E
a
a
1
0
E
T
E
T
Fabcbdcd
1
0
1
0
21
Minimization of BDD
F
b
T
c
E
d
E
T
a
1
0
E
T
Fabcbdcd
1
0
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Realization of the BDD by the pass-transistor
design
a
VDD
E
T
1
0
Fabcbdcd
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Realization of the BDD by the pass-transistor
design
F
b
T
E
c
E
T
d
E
T
a
1
0
F
E
T
Fabcbdcd
1
0
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Realization of the BDD by the pass-transistor
design
Fabcbdcd
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Conclusion

• Pass-Transistor logic design has an extremely
  simple cell library - just one multiplexer
• BDD representation gives pass-transistor design a
  powerful synthesis tool
• BDD also provides a rule to judge in which
  situation we should use pass-transistor logic
  design and in the other case we should use CMOS.