ASIC 120: Digital Systems and Standard-Cell ASIC Design

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ASIC 120 Digital Systems and Standard-Cell ASIC
Design

• Tutorial 4 Digital Systems Concepts
• November 16, 2005

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Outline

• Summary of previous tutorial
• The FPGA LEs, buffers and routing
• Other FPGA resources clocks, memories, memory
  interfaces, multipliers, etc.
• Soft- and hard-processors in FPGAs
• Bus interfaces
• Register files

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Summary of Previous Tutorial

• Other signal values besides 0 and 1
• More VHDL data types
• Attributes, type definitions
• Generics
• Splitting a VHDL project across multiple design
  units and files
• if generate, for generate
• VHDL 1987 vs. 1993 vs. 2000
• Test benches
• time, procedures, variables, file access, etc.

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The FPGA

• FPGA stands for Field Programmable Gate Array
• reprogrammable hardware
• FPGAs contain
• Logic Elements (LEs) which do calculations
• Routing resources between LEs
• Other specialized functions (memory, multipliers,
  etc.)

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The FPGA Origins

• The FPGA is the latest in the family of
  Programmable Logic Devices (PLDs)
• First came the Programmable Logic Array (PLA) or
  Programmable Array Logic (PAL)
• implements combinational (non-clocked) logic
  using array of AND and OR gates
• hundreds to thousands of gates
• Then, the Complex Programmable Logic Device
  (CPLD)
• ability to do sequential circuits
• unlike FPGAs, non-volatile
• thousands to tens of thousands of gates
• Field Programmable Gate Array (FPGA)
• tens of thousands to millions of gates
• often include other resources besides pure logic

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FPGA vs. ASIC

• FPGA
• reprogrammable
• cheap in small quantities
• ASIC
• mistakes are costly and time consuming to fix
• cheap in large quantities
• better power consumption
• smaller for same functionality

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FPGA vs. PSoC or SoC

• System on a Chip (SoC) or System on a
  Programmable Chip (PSoC)
• Integrates several functional blocks onto one
  silicon wafer
• Could include
• Microprocessor
• RAM, ROM, EEPROM
• USB interface
• Ethernet interface
• Graphics controller
• DSP
• etc.

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FPGA vs. PSoC or SoC

• SoC is implemented in an ASIC
• PSoC is implemented in an FPGA
• Another alternative Structured ASICs
• Pre-fab ASICs that take a design implemented and
  tested in an FPGA and put it into an ASIC
• Example Altera HardCopy and HardCopy II
• http//altera.com/products/devices/hardcopyii/hr2-
  index.jsp
• Features
• Power usage and speed characteristics of an ASIC
• Time from order to production can be as fast as
  several weeks (as opposed to months for an ASIC)
• Cost savings

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The FPGA
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The FPGA
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The FPGA
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An FPGA Datasheet

• Datasheets of any ASIC contain detailed
  specifications and technical data
• FPGAs are no exception
• Before you start any design, know the FPGA
  resources
• size limitations
• speed limitations
• number of I/O pins
• clock pins and resources
• special features
• You can never have enough FPGA resources

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Components of an FPGA

• Logic Elements (LEs)
• Routing
• Input/Output logic
• Extra features
• clocking
• memory
• memory interfaces
• multipliers

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The Logic Element

• Two main parts
• Look-Up Table (LUT)
• Flip Flop (FF)
• Other characteristics
• load/clear logic
• carry chain logic
• LUT/FF bypass logic
• clock enable
• other routing

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The Logic Element

• Look-Up Table
• generally four inputs and one output
• can implement any four input boolean expression
• LEs maintain their configuration while power is
  applied to the FPGA
• need to be re-programmed after power-up or global
  reset, and before using

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Routing

• Routing logic connects LEs to
• other LEs
• specialized FPGA resources
• input/output pins
• Different kinds of routing logic
• short lines
• long lines
• carry chains
• clock routing

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How a Design Goes from VHDL to FPGA

• Synthesis ( compilation)
• VHDL to intermediate representation
• Translate
• intermediate representation mapped to LUTs and
  FFs
• Map
• fit translated design into available resources on
  FPGA
• Place and Route
• place mapped LUTs and FFs into locations on FPGA
• determine best routing subject to timing
  constraints
• Programming
• generate a bit stream (binary file) which can be
  loaded into the FPGA at programming time

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How a Design Goes from VHDL to FPGA

• This entire process is extremely
  non-deterministic
• much more so than software compilation
• Terms and steps on previous slide are generic
• individual FPGA companies have their own terms
  and slightly different design flows

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Input/Output Logic

• I/O buffers
• input
• output
• tri-state (output enable)
• Specialized I/O
• memory interfaces
• high speed differential signalling
• Modern FPGAs can be wired directly (with
  appropriate analog support components) to
• RAM chips
• 10/100/1000Base-T Ethernet
• SD-SDI, HD-SDI drivers (up to 1.5 Gbps)
• etc.

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Extra FPGA Features

• Clock features
• Phase/Delay Locked Loops (PLLs/DLLs)
• Special routing resources
• Memory
• Block RAM
• Distributed RAM
• Memory interfaces
• SD-RAM, DDR, DDR2, etc.
• Configuration devices
• Multipliers

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Clocks

• Modern FPGAs feature multiple onboard PLLs that
  can be used for
• phase/frequency synchronization
• frequency multiplication
• arbitrary duty cycles
• Clock routing logic
• dedicated clock lines that run to all LEs
• reduce clock jitter and skew
• Generally external clocks must be connected to
  one of several special pins to use these features

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Memory
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Block RAM
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Distributed RAM
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RAM Inference
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Memory Interfaces
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FPGA Configuration

• What happens to an FPGA on power-up?
• LEs and RAM values are random, or some
  initialization value such as all 0
• An FPGA must be configured before it can be used
• Configured by a microprocessor
• Dedicated configuration device
• CPLD using a non-volatile Flash RAM device

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Multipliers
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Hard- and Soft-Processors
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Soft Processor ExmpleAltera NIOS-II
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Hard Processor ExamplePowerPC
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Interfacing with FPGA Features in VHDL
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Buses

• A bus allows multiple entities to communicate
  over the same wires
• External buses interface between physical ASICs
  or FPGAs
• Internal buses interface between different
  components within an ASIC or FPGA

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An Idle Bus
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Bus Read Cycle
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Bus Write Cycle
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External Bus Interfaces
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Internal Buses

• Separate read and write buses

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Buses What Ive Skipped

• Bus arbitration
• multiple masters
• Direct Memory Access (DMA)
• Bus mastering
• See the ECE 324 course notes for more on buses

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Register Files

• Also called register blocks

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What Ive Skipped

• Blocks, Libraries/Packages
• other modularity features
• weve had a taste of libraries and packages
• library ieee
• Configurations
• way to select among multiple architectures
• Constants
• like generics, but within one file
• File access
• useful for test benches, not synthesizable
• Functions, procedures, variables

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Preview of Next Tutorial

• Digital Systems Concepts
• The FPGA LEs, buffers and routing, other
  resources
• Bus interfaces
• Register files
• Other FPGA resources clocks, memories, memory
  interfaces, multipliers, etc.
• Soft- and hard-processors in FPGAs

43
Summary

• Summary of previous tutorial
• Other signal values besides 0 and 1
• More VHDL data types
• Attributes, type definitions
• Generics
• Splitting a VHDL project across multiple design
  units and files
• if generate, for generate
• VHDL 1987 vs. 1993 vs. 2000
• Test benches
• time, procedures, variables, file access, etc.

44
UW ASIC Design Team

• www.asic.uwaterloo.ca
• reference material
• Accolade VHDL reference (excellent!)
• http//www.acc-eda.com/vhdlref/
• many of todays examples came from here
• Bryce Leungs tutorials (UW ASIC website)
• Mike Goldsmiths tutorials (UW ASIC website)
• your course notes
• my contact info
• Jeff Wentworth, jswentwo_at_engmail.uwaterloo.ca