GaAs HBT PA Design and SiGe HBT Device Modeling

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GaAs HBT PA Design and SiGe HBT Device Modeling
Brendan Crooks Bimonthly Progress Report January
14, 2004
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Accomplished Tasks

• GaAs HBT Power Amplifier Design
• Pre-layout design has been made with ideal
  passive elements.

• SiGe HBT Device Modeling
• Models have been found for all 8 Devices

Unaccomplished Tasks What still needs to be done

• GaAs HBT PA Design
• Literature study and implementation of active
  bias circuits
• Design of on-chip matching networks
• Optimization of PAE with respect to base bias
  currents

• SiGe HBT Device Modeling
• Analysis of models found
• Literature study of distortion in SiGe devices
  and how IP3 measurements are made
• Take IP3 measurements for each device
• Analysis of results

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Results of Accomplished Task 1
Summary of Prelayout Simulation Results for
3-Stage GaAs PA
Center Frequency 5.8 GHz VSUPPLY 3.0V Output
Power (Saturated) 33.2 dBm Output Power (1-dB)
31.4 dBm Transducer Gain 38.6 dB PAE
(maximum) 51.4 PAE (1-dB) 29.3 ISUPPLY
1.56A   Intermodulation Products   OIP3 51
dBc OIP5 46 dBc
Harmonics   2nd Harmonic 36.5 dBc 3rd
Harmonic 37.7 dBc 4th Harmonic 46.5 dBc 5th
Harmonic 55.1 dBc   S-Parameters   S11
-32.9 dB S22 -17.5 dB S12 -104.1 dB S21
39.8 dB
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Results of Accomplished Task 1 (contd)
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Results of Accomplished Task 1 (contd)
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Results of Accomplished Task 1 (contd)
Block Diagram of 3-Stage PA
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Results of Accomplished Task 1 (contd)
Circuit Diagram of 3-Stage PA
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Results of Accomplished Task 2
Circuit Diagram of SiGe HBT Model
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Results of Accomplished Task 2 (contd)
Circuit Diagram of Intrinsic Model
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Results of Accomplished Task 2 (contd)
Summary of SiGe HBT Model Values
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Results of Unaccomplished Tasks and Proposals

• GaAs HBT PA Design
• Optimization of PAE with respect to base bias
  currents
• Class A operation is not very efficient.
  Reducing the bias current will improve
• PAE. This will require another iteration of my
  design.
• Literature study and implementation of active
  bias circuits
• I have some good papers on bias circuitry for
  GaAs HBT Power Amplifiers.
• I would like to integrate this type of biasing
  into my design
• Design of on-chip matching networks
• This cannot be done until the rest of the items
  above have been completed.
• Layout of circuit

• SiGe HBT Device Modeling
• Analysis of model results with some guidance
  from Arvind
• Literature study of distortion in SiGe devices
  and how IP3 measurements are made
• Take IP3 measurements for each device
• Analysis of results

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Proposals for the Next Two Weeks

• GaAs HBT PA Design over the next two weeks I
  will be focusing on the GaAs PA design so that it
  can be sent out to be fabricated as soon as
  possible. I plan to complete the prelayout
  design in the next two weeks. If I finish
  sooner, I will begin on the layout. Completing
  the design will entail the following
• Optimization of PAE with respect to base bias
  currents This will involve adjusting the bias
  current until the PAE is maximized.
• Implementation of active bias circuits Once the
  optimum bias current is known, the bias circuits
  can be designed accordingly.
• Design of on-chip matching networks The design
  guide in ADS can assist in determining which
  on-chip components will give the best match.
• SiGe HBT Modeling work with Arvind to analyze
  the results of the HBT Modeling