Flip-Flop Circuits CPEG 324

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Flip-Flop CircuitsCPEG 324
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Inverter
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Bistable element
HIGH
LOW
LOW
HIGH
LOW
HIGH
HIGH
LOW
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Analog analysis

• Assume pure CMOS thresholds, 5V rail
• Theoretical threshold center is 2.5 V

2.5 V
2.5 V
2.51 V
2.0 V
4.8 V
0.0 V
5.0 V
2.5 V
2.5 V
2.0 V
4.8 V
0.0 V
5.0 V
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Metastability

• Metastability is inherent in any bistable circuit
• Two stable points, one metastable point

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Another look at metastability
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Why all the harping on metastability?

• All real systems are subject to it
• Problems are caused by asynchronous inputs that
  do not meet flip-flop setup and hold times.
• Especially severe in high-speed systems
• since clock periods are so short, metastability
  resolution time can be longer than one clock
  period.
• Many digital designers, products, and companies
  have been burned by this phenomenon.

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Pass Transistor
VIN
VOUT
C
When C1, then VIN VOUT or Electrical Short
VOUT
VIN
When C0, then Electrical Open between VIN and
VOUT
VOUT
VIN
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D Latch

• Feedback inverter (X) is weak
• When C1, D will overpower X and force QD.

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D-latch operation
latch acts like a wire while its control is
active flip-flop (later) grabs data when control
changes
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D-latch timing parameters

• Propagation delay (from C or D)
• Setup time (D before C edge)
• Hold time (D after C edge)

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D Flip-Flop based on Bistable Element
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D Flip-Flop Operation
latch acts like a trigger at the rising edge of
CLK it grabs data (D) and stores it (Q).
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D flip-flop timing parameters

• Propagation delay (from CLK)
• Setup time (D before CLK)
• Hold time (D after CLK)

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Example RT54SXS Flip-Flop
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Hand-Drawn Metastability Example
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Metastability - Introduction

• Can occur if the setup, hold time, or clock pulse
  width of a flip-flop is not met.
• A problem for asynchronous systems or events.
• Can be a problem in synchronous systems.
• Three possible symptoms
• Increased CLK -gt Q delay.
• Output a non-logic level
• Output switching and then returning to its
  original state.
• Theoretically, the amount of time a device stays
  in the metastable state may be infinite.
• Many designers are not aware of metastability.

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Metastability

• In practical circuits, there is sufficient noise
  to move the device output of the metastable state
  and into one of the two legal ones. This time
  can not be bound. It is statistical.
• Factors that affect a flip-flop's metastable
  "performance" include the circuit design and the
  process the device is fabricated on.
• The resolution time is not linear with increased
  circuit time and the MTBF is an exponential
  function of the available slack time.

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Metastable StatePossible Output from a Flip-flop
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Metastable StatePossible Outputs from a
Flip-flop
Correct Output
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Metastability