Adaptive Data Analysis and Processing Technology (ADAPT)

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Adaptive Data Analysis and Processing Technology
(ADAPT)

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Reconfigurable Computers for Spacecraft Use

• Adapt to changing mission requirements after
  launch
• Reduce spacecraft resources for onboard storage
  and downlink from high data bandwidth instruments
  by reducing data rates from the instruments
• Hardware fabrication before algorithms are
  completed
• Update or correct algorithms after launch
• Reduce engineering set up times for science
  observatoriesReduced setup times
• FPGAs offer high performance and processing power
  
• Physical design remains the same easily tailor
  control and data interfaces
• Minimizes instrument and system development time
• Mitigates hardware and software errors in flight
• Multiple configurations can be stored for rapid
  adaptations

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AIM 1st Demonstration Reconfigurable Computing
in Space

• FedSat-1 50 kg microsatellite, LEO 1000 km
  altitude
• Adaptive Instrument Module (AIM) - Precursor to
  ADAPT
• Includes an 80C196 processor and a Xilinx XQR4062
  FPGA that performs reconfigurable processing
• 890 grams, dissipates lt 2 W
• Launched December 14, 2002 on Australian FEDSAT
• AIM partners - APL, Queensland University of
  Technology, Goddard Spaceflight Center, and
  Langley Research Center

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Challenge

• Challenges for effective use in spacecraft
• Configuration Memory Upsets SRAM-based FPGAs are
  susceptible to radiation-induced upsets in
  configuration memory. The frequency of these
  upsets must be investigated, and techniques
  developed to detect and correct them.
• Management of Multiple Configurations Spacecraft
  have limited onboard resources and limited
  communications to ground stations. Techniques for
  managing the configuration data for FPGAs onboard
  a spacecraft will be very different than ground
  applications. These techniques need to be
  investigated, developed and analysed.
• Prototype Demonstration A prototype AIM needs to
  be flown as a standalone experiment on a space
  mission to validate the initial design decisions
  made and evaluate improvements in satellite
  performance.

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Requirements

• Implement a low cost, radiation hardened,
  reconfigurable processor for Fedsat-1 and other
  spacecraft
• Use Xilinx XQR4062 FPGA as the heart of the
  reconfigurable processor
• Store and manage multiple Xilinx FPGA
  configurations
• Able to upload additional configurations
• Detect, correct, and log single event upset
  induced configuration errors autonomously in the
  Xilinx FPGA
• Run standalone reconfigurable computing
  experiments
• Process instrument data with reconfigurable
  hardware
• Interface to spacecraft command and data handling
  system
• Generate voltages from spacecraft 28V bus

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Design

• The AIM consists of the following components
• A 62,000 gate SRAM-based FPGA ( Xilinx
  XQR-4062XL)
• A 16-bit microcontroller ( UTMC UT80C196KD)
• 512 kbytes of EEPROM to hold microcontroller boot
  and application code
• 8 Mbytes of non-volatile Flash to hold
  configurations for the Xilinx
• 1 Mbyte of SRAM for microcontroller program and
  data
• 0.5 Mbytes of SRAM for Xilinx data processing
  memory
• An RS422 serial port for communication with the
  satellite command data handling system
• An uncommitted communications port connected
  directly to the Xilinx, to be configured on a
  mission-by-mission basis.
• Power converter circuitry to provide 3.3V and 5V
  from 28V
• Voltage and Temperature status lines

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AIM Flight Module Area Study

• Flight Unit Characteristics
• Weight estimated 1 kg
• Size 16 cm x 17.5 cm x 3.0 cm
• Power 2.5W (from 28V)
• Parts selected for radiation tolerance and
  availability
• Xilinx XQR4062XL - 62,000 gate SRAM-based FPGA
• UTMC UT80C196KD 16-bit microcontroller
• SEI 28C010TRPFB-15 512Kx8 EEPROM
• SEI 29F0408RP 4Mx8 Flash
• Austin/Motorola 5C512K8F 512Kx8 SRAM
• Actel A1280A fuse link FPGA

145 mm (5.65 in)
175 mm (6.83 in)
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AIM Flight Unit Test
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ADAPT Objectives

• Develop a prototype reconfigurable processor
  utilizing state-of-the-art Field Programmable
  Gate Array technology
• Develop algorithms that meet the requirements for
  two Earth Science Enterprise mission scenarios
• Microwave Radiometers
• Fourier Transform Spectrometers (FTS)
• Design, fabricate, and test a flight-grade
  reconfigurable processor
• Demonstrate algorithms using flight-grade
  reconfigurable processor

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ADAPT Hardware Design- commercial standards

• Xilinx Virtex II FPGA (XC2V1000)
• Equivalent of 1 million gates and 720k bits of
  RAM
• 40 Dedicated 18x18 Multipliers (300 MHz)
• A wide range of IP cores are available
• DSP functions
• Processors
• Math functions
• New designs can be implemented with a wide range
  of development tools

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ADAPT - Hardware Definition

• ADAPT stores multiple FPGA configurations in
  flash memory.
• Instrument processing algorithms can be changed
  in real time.
• Fuse-programmed Actel FPGA implements the system
  interface
• Host processor chooses configurations for the
  Xilinx Virtex II FPGA.
• Operation
• Host selects configuration
• Second Actel FPGA reads back and verifies
  configuration of Xilinx FPGA
• Automatically corrects the configuration and
  notifies the host processor when it detects
  discrepancies.
• Xilinx FPGA connects to external SRAM memory to
  store intermediate results, coefficients, and
  variables
• Voltage regulators supply the low-voltage
• Backplane supplies standard 3.3 and 5V power
• Xilinx clock may derive from
• on-board oscillator
• the PCI bus clock
• or from the I/O connector
• Xilinx FPGA on-chip temperature sensor routes to
  I/O connector.
• Instrument data flow through
• PCI bus
• I/O connector

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ADAPT Board Block Diagram
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ADAPT Breadboard
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ADAPT Configuration Manager

• Implemented in Actel 54SX32 radiation hardened
  FPGA
• Hardware Triple-Voted S-Modules
• Runs at 50MHz
• VHDL Design
• modeled after C program which was initially used
  to verify the config/readback scheme

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ADAPT Configuration Manager
Flash Memory Interface
Data to PCI Actel
State Machine
Xilinx SelectMap Interface
Commands from PCI Actel
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ADAPT Configuration Manager Modes
If all goes well
START(IDLE)
Xilinx configuration UPLOAD
Xilinx Continuous Frame-wise readback
error
On Command Through PCI Host Actel
During frame-by-frame readback, Contents of each
frame are compared With contents of rad-hard
Flash. (Mask and config bits are interleaved)
Configuration occurs frame by frame As opposed to
normal Xilinx Upload This allows data structure
stored in Memory to be the same for readback
/ SEU correction.
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ADAPT Configuration Manager Modes
Put Xilinx back into write mode
Write Corrected Frame, Pad Pipeline
Switch Xilinx back to read Mode
Signal PCI Host Interface which makes IRQ
Manager continues reading where it left off
before encountering SEU
Xilinx Active Partial Reconfiguration is used,
new configuration frame is uploaded while the
device is operating. Xilinx experiences no
operation interruption
Times Programming 100 ms Roundtrip Readback
200 ms
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ADAPT Host Interface FPGA

• Implemented in Actel 54SX32
• Uses Actel IP PCI Core v 5.2.1
• APL is targetting this core for other space
  missions
• some corrections incorporated
• bug fixes
• workarounds for Actel timing hazards as they are
  discovered.
• 33 MHz, 32-bit PCI Target Only

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ADAPT Host Interface FPGA
To Config Manager
Flash Control / Data
To 3V Compact PCI Backplane
PCI Interface
Config Manager Control / Status
To Xilinx
Write - Fifo
Interrupt (currently Associated with SEU
Detection)
Read - Fifo
From Xilinx
under development
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ADAPT Usage Flow Software

• Design Xilinx using ISE Foundation Toolset
• Use Rad-tolerant techniques to protect RAM and
  flipflops
• Use ADAPT compiler and linker to generate files
  suitable for residing in flash memory
• Use ADAPT flash-software to program flash from
  flashfile.
• Send command through PCI interface to start
  (configure) Xilinx with a particular config from
  flash.
• If option is enabled, SEU mitigation will proceed
  immediately upon successful configuration
• Status of configuration / readback process can be
  read through software driver.

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Upcoming Test / Refinements

• Testing of Host Interface FIFOs to allow Xilinx
  to send data via PCI if desired
• Make slight modification to Compiler / Linker to
  store multiple configurations in Flash
• Packaging Software into a more user-friendly
  installation package
• Simulation of SEU in Xilinx FPGA
• Environmental tests
• Radiation tests

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Example of ADAPT Instrument

• ADAPT will implement real time data reduction,
  compression, and feature extraction algorithms.
• Minimizes spacecraft resources
• onboard data storage
• downlink bandwidth
• Generic design can be used for different
  instruments

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Microwave Radiometer Digital I Q
QX
Digitized Radiometer Signal (6-bit data)
IX
64 MHz data rate
32 MHz data rate
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Microwave Radiometer Digital Correlator
ADAPT BOARD
MAC I1xI1 I1xQ2 Q1xQ1 Q1xI2
I2xI2 I2xI1 Q2xQ2 Q2xQ1 (0.1 sec Integration
Period)
Digital I Q
I1
Ch 1, 6-bit data
Q1
Parallel-to-Serial Converter/Multiplexer
Serial Output
Ch 2, 6-bit data
Digital I Q
I2
Q2
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Microwave Radiometer Interface Hardware
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FTS Motion Control Application
VHDL-coded 16-bit Motion Controller for Fourier
Transform Spectrometers
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FTS System
GSE Data Collection
ADC 18-bits
IR Detector
Laser Detector
Motion Control
Velocity ? Spectral Resolution
(0.25 cm-1)
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Control Configuration
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? Compensator
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(-)
CNTin
21
20
40
16
16
PID
Latch
DAC
CLAMP
CLAMP
TCtoMO
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CNTfbk
Tc
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Electronics
D2
1
2
1N4742
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Resource Utilization for Xilinx Virtex-II Million
Gate Device

• Number of Slices
• 324 out of 5,120 6
• Number of Flip Flops
• 182 out of 10,240 1
• Number of LUTs
• 592 out of 10,240 5

RMS Velocity Error
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Use of ADAPT Technology in IIP
3U CompactPCI Chassis
Stepper Motor for Scene Selection Mirror
4-Axis Controller
HRE Etalon Control Electronics
HRE Etalon
PZT Control
CompactPCI Bus
Capacitive Sensor Feedback
4-Axis Controller
LRE Etalon Control Electronics
LRE Etalon
PZT Control
1.26 GHz PXI Embedded Controller
Capacitive Sensor Feedback
Readout Integrated Circuit
FPA
Pixel Binning and Frame Averaging Electronics
IDE Interface
Analog Inputs (Housekeeping Parameters)
Solid State Disk (OS, Program files, etc.)
Analog Interface Electronics
16-Channel A/D
73 GB Rugged Removable Hard Drive
SCSI Interface
Real-Time Display/ User Interface Computer
Ethernet Interface
GPS Interface
Yellow Performed by ADAPT hardware
Green Could be performed with ADAPT hardware
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Accomplishments

• Developed a simplified technique for
  partial-reconfiguration (SEU correction)
• Efficient format for storing configuration/readbac
  k data in flash memory developed (3 x reduction
  in memory over standard bitstream format)
• Convert Xilinx bitstream files to ADAPT
  formatFabricated ADAPT board
• Completed design/assembly/test of test-adapter
  board that allows software driven testing of
  Xilinx configuration interface
• Demonstrated configuration / active readback /
  partial active reconfiguration (correction) Host
  Actel designed and tested
• Developed Host Software
• Linux Device Driver
• Bitfile Compiler / linker
• Flash erase / program / verify
• Configuration Loader
• Demonstrated upload,readback, partial
  reconfiguration under Actel control