Advances in 1/f noise modeling: 1/f gate tunneling current noise model of ultrathin Oxide MOSFETs

1
Advances in 1/f noise modeling 1/f gate
tunneling current noise model of ultrathin Oxide
MOSFETs
F. MARTINEZ, M.VALENZA
Institut dÉlectronique du Sud CEM2 UMR 5507,
Place E.Bataillon, U.M. II, 34095 Montpellier
Cedex 5, France.
Institut dÉlectronique du Sud
UMR 5507
2
Introduction

• Reduction of oxide thickness ? Increase of gate
  leakage current
• Limitation of classical characterization methods
• New noise sources
• Low-frequency noise is a very sensitive tool for
  probing slow oxide traps
• The gate to channel current noise must be taken
  into account in the MOSFET noise
  characterization.
• We will show that our 1/f gate noise model can be
  applied to
• the characterization of slow oxide traps
• compact noise modeling of MOSFETs
• The off state drain current is dominated by the
  overlap gate leakage current
• What about the overlap gate current LF noise ?

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Outline

• Introduction
• Gate current low-frequency noise model and
  characterization
• Drain and gate current LFN Comparison
• Contributions of Channel Gate and Overlap Gate
  Currents on 1/f Gate Current Noise
• Conclusion

4
Gate current LF Noise Measurements
Experimental Set-Up
Trans-impedance AMPLIFIER
VGS
HP89410A
VDS
A
TRANSISTOR
ANALYSER
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Typical Gate Noise PSD

• 1/f noise level extracted at 1 Hz
• RTS noise observed on Gate current

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1/f Oxide Trapping noise Model

• Trapping Detrapping model (McWhorter)

EC
Ei
EFn
EV
q
EC
q
qVGB
EF
EV
SiO2
n Poly
p Substrate
y
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1/f Gate Current Noise Model
Fluctuation of the number of filled traps
Fluctuation of the Flat Band Voltage
Gate Current Fluctuations
Power Spectral Density of gate current noise
Power Spectral Density of gate current noise VDS
0 V and homogeneous structure
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Devices Under Test
nMOS Transistors 65 nm CMOS Technology

• Nitrided gate dielectric EOT 1.2 nm
• DPN process (Plasma Nitridation)
• n Polysilicon Gate (1200 Å)
• Isolated Devices with Individual Electrodes
• Constant Width of 10 µm
• L ranging from 40 nm to 10 µm

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1/f Gate Current Noise ModelExperimental
Validation
Slow Oxide trap density extracted from Low
frequency gate noise measurements
NT (EF) ? 1 1018 cm-3 eV-1
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Impact of Drain Voltage on LF Gate Current Noise
nMOS W / L 10 / 0.2 µm
There is no low-frequency induced gate noise from
channel current noise
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Gate RTS Noise
Time and Spectral signature of Oxide Single Defect
Single defect characterisation by RTS Gate
current noise measurements
W / L 10 / 10 µm No RTS noise observed on Drain
Current RTS noise observed on Gate Current
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Gate RTS Noise
S.R.H. Statistics
Surface Potential Model
xt (nm) ET0 (eV) DEB (eV) s0 (cm²)
0.1 2.95 0.4 5 10-20
Typical Characteristics of Nitrogen-related
Trap (C. Leyris WoDim 2006)
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Outline

• Introduction
• Gate current low-frequency noise model and
  characterization
• Drain and gate current LFN Comparison
• Contributions of Channel Gate and Overlap Gate
  Currents on 1/f Gate Current Noise
• Conclusion

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Comparison of SVFB(f) extracted fromDrain and
Gate noise measurements
nMOS W / L 10 / 1 µm Drain Current LF noise
The same Flat Band Voltage fluctuations are
involved in drain and gate current LF noise
nMOS W / L 10 / 1 µm Gate Current LF noise
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Devices Under Test
nMOS Transistors

• Nitrided gate dielectric EOT 12 ?
• RTN process (Rapid Thermal Nitridation)
• n Poly-silicon Gate (1200 ?)

Gate stack
Standard devices Bulk
Strained devices Si0.8Ge0.2
Channel engineering

• Isolated Devices with Individual Electrodes
• Constant Width of 10 µm
• L ranging from 0.04 to 10 µm

Devices parameters
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Drain current noise measurements
Flat band voltage PSD extracted from drain
current noise in strong inversion regime
-0.8
W/L 10 µm / 0.34 µm

• SVG(f) obtained from the drain noise model are
  independent of the gate biases
• 1/f? behavior is observed
• An average value of ? was found around 0.8
• Trap density exponentially decreases when moving
  away from Si/SiON interface

JAYARAMAN and SODINI, Trans. Electron Devices,
1990
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Gate current noise
Gate current noise level at f 1 Hz for two gate
lengths, VDS 25 mV

• Data are extracted from the strong inversion
  regime
• Levels obtained at f 1 Hz are in good agreement
  with the proposed gate noise model

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Comparison of SVfb(f) from gate and drain current
noise
VDS 25 mV
VGS 0.95 V 10 x 1 µm²
VGS 0.65 V 10 x 0.34 µm²

• Same values of SVfb(f) due to the same trapping
  process are obtained for frequencies below 1 kHz
• Full shot noise (2qIG) dominates the gate noise
  above 1 kHz

The same Flat Band Voltage fluctuations are
involved in drain and gate current LF noise
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Strained-channel vs. standard n-MOSFETs
Normalized Flat band voltage fluctuation PSD SVfb
x W x L extracted from drain and gate current
noise for both strained and standard devices.
VDS 25 mV VGS 0.8 V

• Good accordance of results achieved for several
  gate lengths
• As the same gate stack process was used for both
  architectures
• The slow oxide trap densities involved in LFN are
  not affected by channel engineering

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Impact of Gate LFN on Drain LFN
W / L 10 / 10 µm
Fluctuation Continuity Equation
Drain and Source LFN PSD
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Electrical Modeling of LF Gate Current Noise
SIGD
BSIM4 LF Drain Current Noise Based on DN-Dµ
Model 3 noise parameters NOIA NOIB NOIC NOIA
Nt(EF) in units of J-1 m-3
Gate
Drain
Noiseless MOSFET
SIGS
SID
Source
Source
LF Gate-Source noise model
LF Gate-Drain noise model
Correlation
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Outline

• Introduction
• Gate current low-frequency noise model and
  characterization
• Drain and gate current LFN Comparison
• Contributions of Channel Gate and Overlap Gate
  Currents on 1/f Gate Current Noise
• Conclusion

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p-MOSFET Gate Leakage Current
Saturation Range VDS -1 V
Low drain bias VDS -25 mV
VGS
VGS
VD-25 mV
VD-1V
IGC
IGC
P
P
IGDO
IGDO
P
P
P
P
N
N
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Gate to Channel Current Noise Characterization at
low drain bias
SVFB Extraction
VDS -25 mVGate to Channel leakage
A single value of SVFB x WL allows to simulate
the gate current noise of studied devices
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Gate to Channel Current Noise Characterization in
Saturation Range
VGS
VD-1V
VDS -1 VGate to Channel leakage
IGC
P
Same SVFB x WL Value for Saturation Range
P
P
N
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Gate to Drain Overlap Current Noise
Characterization (1/2)
VGS0
VDS
IGC
P
P
P
N
W/L 10 µm / 1 µm
W/L 10 µm / 10 µm
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Gate to Drain Overlap Current Noise
Characterization (2/2)
Extraction of SVFB for different Widths and L
10 µm
The same Normalized SVFB is used to modelthe
gate overlap current LF noise
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Gate Current Noise (On/Off state)Circuit Design
point of view
W/L 10 µm / 1 µm
W/L 10 µm / 10 µm
VDS -1 V
VDS -1 V
1/f gate noise is higher in the off-state than in
the on-state for short channel devices
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Outline

• Introduction
• Gate current low-frequency noise model and
  characterization
• Drain and gate current LFN Comparison
• Contributions of Channel Gate and Overlap Gate
  Currents on 1/f Gate Current Noise
• Conclusion

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Conclusion

• The 1/f gate current noise model involves slow
  oxide traps
• Extraction of slow oxide trap densities by gate
  current noise measurements
• Good agreement with slow oxide trap densities
  extracted from drain current noise
• The same Flat Band voltage fluctuations are
  involved in both gate and drain LF noise
• For short channel devices, gate current LF noise
  can be higher in the off-state than in the
  on-state.
• Implantation in MOSFET compact model
• Formulation with NOIA BSIM4 noise parameter and
  gate LF noise partition