Chapter 3 Memory System Design and Interfacing

1
Chapter 3Memory System Design and Interfacing
2
3.1.1 Access/Cycle times and memory bandwidth

• Memory access time ta
• the time between the receipt by memory of the
  address bits (or READ command) and memorys
  response by driving its valid output on the data
  bus lines
• Memory cycle time tc
• The minimum interval between two consecutive
  requests for a read operation
• RAM/ROM access time equals to cycle time
• DRAM cycle time is twice the access time
• Memory writes time is often little than the
  memory read time

3

• Memory bandwidth maximum amount of information
  that can be transferred to and from memory every
  second
• Bandwidth b w/tc bits/sec
• The memorys bandwidth is usually smaller than
  the microprocessor, how to increase the memory
  bandwidth?
• Design faster memory chips
• Design wider memory
• Design advance access modes (nibble, static
  column, burst transfer, etc0
• Memory hierarchical design (cache system)
• Memory interleaving

4
????
5
????

• ??????,????????????,????????
• ????????,?????????????,???????
• ??????
• ?????????????????
• ?????????????????

6
3.1.3 Static and Dynamic RAMs
7
Interface to SRAMs
8
Interface to SRAMs
9
DRAM internal structure

• This is a 256 K 1-bit DRAM chip
• it is arranged as a square array of 512 rows and
  512 columns
• If we need to form a 32-bit memory, we would have
  to use 32 of these DRAMs
• The address pins of a DRAM chips is equal to the
  half the size of the total address

10
Timing diagram of the DRAM

• Random cycle time (TRC)
• Minimum time between any two successive reads
  (1/TRC is bandwidth)
• Access time from RAS (TRAC)
• The time interval from asserting the RAS until
  the chip outputs its data
• Precharge time (TPR)
• During every bus cycle the DRAM chips will have
  to recharge before the processor can use them
  again
• The precharge time is different from the refresh
  period
• Cycle time access time precharge time
  2access time
• EX 50 ns DRAM means
• access time 50 ns ? cycle time 100 ns ?
  bandwidth 1/100 ns 10 Mbit/sec

11
DRAM Read Operation Timing
12
DRAM Write Operation Timing
13
Refreshing DRAMs

• DRAM uses single transistor cell to store data ?
  DRAM require special external circuits, counters
  (rows, columns), and high-voltage pulses to
  refresh memory periodically
• The external refresh circuitry must access each
  row once within each refresh time interval
• The common refresh frequency is about 4 ms
• Need arbitration circuitry at the memory
  interface to deal with simultaneous requests for
  access from the processor and from the refresh
  circuitry
• The refresh will adds a performance overhead of
  between 6 and 12

14
3.1.4 Memory Organization

• Address space
• Memory address space v.s. I/O address space
• Logical address space v.s. physical address space
• Memory wordlength
• The byte is the basic addressable element and the
  smallest unit of information transferred with
  each access
• Data element or instructions of 16 bits or longer
  may be placed in memory starting at any byte
  address (alignment problem), and are referenced
  using an address that designates their first byte
  in memory (this byte is the most significant or
  the least significant byte depends on the
  endianess of the stored operation)

15
Address space allocated to the local and system
bus
16
Ex 3.4 decode 24-bit address space to local bus
(0 14 Mbyte) and system bus (15th Mbyte)
17
3.2 Designing the memory subsystem

• Ex 3.5 24-bit address, 8-bit data bus, 64 K
  8-bit memory module

18
Forming the wordlength of the target memory