ELEN 468 Advanced Logic Design

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ELEN 468Advanced Logic Design

• Lecture 14
• Synthesis of Sequential Logic

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Synthesis of Sequential Logic General

• Event control of a cyclic behavior must be
  synchronized to a single edge of a single clock
• always _at_ ( posedge clock )
• Different behaviors may be synchronized to
• different clocks
• or different edges of a clock
• but clock periods should be same

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Options for Implementing Sequential Logic

• User-defined primitive
• Behavior with timing controls
• Instantiated library register cell
• Instantiated module

4
Commonly Synthesized Sequential Logic

• Data register
• Transparent latch
• Shift register
• Binary counter
• Finite state machine
• Pulse generator
• Clock generator
• Parallel/serial converter
• Table 9.2, page 346

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Synthesis of Sequential UDPs

• Only one synchronizing signal
• Clock level latch
• Clock signal edge flip-flop
• A synthesis tool may have its own requirement
• For example, may constrain the order of rows
  asynchronous first

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Example of Sequential UDP

• primitive d_flop( q, clock, d )
• output q
• input clock, d
• reg q
• table
• // clock d state q/next_state
• (01) 0 ? 0 // Parentheses indicate
  signal transition
• (01) 1 ? 1 // Rising clock edge
• (0?) 1 1 1
• (0?) 0 0 0
• (?0) ? ? - // Falling clock edge
• ? (??) ? - // Steady clock
• endtable
• endprimitive

clock
d
q
d_flop
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Synthesis of Latches

• Latches are incurred at
• Incompletely specified input conditions for
• Continuous assignment -gt mux with feedback
• Edge-triggered cyclic behavior -gt gated datapath
• Level-sensitive cyclic behavior -gt latch
• Feedback loop

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Latch Resulted from Unspecified Input State

• module myMux( y, selA, selB, a, b )
• input selA, selB, a, b
• output y
• reg y
• always _at_ ( selA or selB or a or b )
• case ( selA, selB )
• 2b10 y a
• 2b01 y b
• endcase
• endmodule

b
selA
en
selB
y
selA
latch
selB
a
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Latch Resulted from Feedback Loop

• module latch1 ( out, in, enable )
• input in, enable,
• output out
• reg out
• always _at_ ( enable )
• begin
• if ( enable )
• assign out in
• else
• assign out out
• end
• endmodule

enable
in
out
mux
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Synthesis of Edge-triggered Flip-flops

• A register variable in a behavior might be
  synthesized as a flip-flop if
• It is referenced outside the scope of the
  behavior
• Referenced within the behavior before it is
  assigned value
• Assigned value in only some branches of the
  activity

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Event Control Sensitive to Multiple Signal Edges

• module DReg ( out, in, clock, reset )
• input in, clock, reset
• output out
• register out
• always _at_ ( posedge clock or posedge reset )
• begin
• if ( reset 1b1 ) out 0
• else out in
• end
• endmodule

An if statement decode control signals at the
beginning of the behavior
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Registered Combinational Logic

• module reg_and ( y, a, b, c, clk )
• input a, b, c, clk
• output y
• reg y
• always _at_ ( posedge clk )
• y a b c
• endmodule

clk
a
y
b
c
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Shift Register

• module shift4 ( out, in, clock, reset )
• input in, clock, reset
• output out
• reg 30 data_reg
• assign out data_reg0
• always _at_ ( negedge reset or posedge clock )
• begin
• if ( reset 1b0 ) data_reg 4b0
• else data_reg in, data_reg31
• end
• endmodule

Figure 9.10, page 361
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Counter

• module ripple_counter ( count, clock, toggle,
  reset )
• input clock, toggle, reset output 30
  count
• reg 30 count wire c0, c1, c2
• assign c0 count0 assign c1 count1
  assign c2 count2
• always _at_ ( posedge reset or posedge clock )
• if ( reset 1b1 ) count0 1b0
• else if ( toggle 1b1 ) count0
  count0
• always _at_ ( posedge reset or negedge c0 )
• if ( reset 1b1 ) count1 1b0
• else if ( toggle 1b1 ) count1
  count1
• always _at_ ( posedge reset or negedge c1 )
• if ( reset 1b1 ) count2 1b0
• else if ( toggle 1b1 ) count2
  count2
• always _at_ ( posedge reset or negedge c2 )
• if ( reset 1b1 ) count3 1b0
• else if ( toggle 1b1 ) count3
  count3
• endmodule

Fig. 9.14 Page 366
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Synthesis of Explicit Finite State Machines

• A behavior describing the synchronous activity
  may contain only one clock-synchronized event
  control expression
• There is always one and only one explicitly
  declared state register
• State register must be assigned value as an
  aggregate, bit select and part select assignments
  to state register is not allowed
• Asynchronous control signals must be scalars in
  the event control expression of behavior
• Value assigned to state register must be constant
  or a variable that evaluates to a constant

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Comparison of Explicit and Implicit FSMs
Explicit FSM Implicit FSM
Explicit State Register Yes No
State Encoding Yes No
Sequence of States Specified Implicit
Sequence Control Explicit assignment to state register Specified by procedural flow
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State Encoding Example
Binary Gray Johnson One-hot
0 000 000 0000 00000001
1 001 001 0001 00000010
2 010 011 0011 00000100
3 011 010 0111 00001000
4 100 110 1111 00010000
5 101 111 1110 00100000
6 110 101 1100 01000000
7 111 100 1000 10000000
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State Encoding

• A state machine having N states will require at
  least log2N bits register to store the encoded
  representation of states
• Binary and Gray encoding use the minimum number
  of bits for state register
• Gray and Johnson code
• Two adjacent codes differ by only one bit
• Reduce simultaneous switching
• Reduce crosstalk
• Reduce glitch

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One-hot Encoding

• Employ one bit register for each state
• Less combinational logic to decode
• Consume greater area, does not matter for certain
  hardware such as FPGA
• Easier for design, friendly to incremental change
  
• case and if statement may give different result
  for one-hot encoding
• Runs faster

• define state_0 3b001
• define state_1 3b010
• define state_2 3b100

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Rules for Implicit State Machines
Synchronizing signals have to be aligned to the
same clock edge in an implicit FSM, the following
Verilog code will not synthesize

• always _at_ ( posedge clock )
• begin
• a lt b
• c lt d
• _at_( negedge clock )
• begin
• e lt f
• g lt h
• end
• end

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Resets

• Strongly recommended that every sequential
  circuit has a reset signal
• Avoid uncertain initial states
• Specification for output under reset should be
  complete, otherwise wasted logic might be
  generated

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Gated Clock

• Pro reduce power consumption
• Con unintentional skew

data
Q
flip-flop
clock
clock_enable
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Design Partitions

• Partition cells such that connections between
  partitions is minimum

1
a
2
b
3
c
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Example Sequence Detector

• Single bit serial input
• Synchronized to falling edge of clock
• Single bit output
• Assert if two or more successive 0 or 1 at input
• Active on rising edge of clock

Clock
Input
Output
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State Transition Diagram
State0 Start state
1/0
0/0
1/1
0/1
1/0
State1 Input 0
State2 Input 1
0/0