Class Presentation on Binary Moment Diagrams by Krishna Chillara Base Paper:

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Class Presentation onBinary Moment Diagramsby
Krishna ChillaraBase Paper Verification of
Arithmetic Circuits with Binary Moment Diagrams
by Randal E. Bryant and Yirng-An Chen
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Outline

• Introduction
• Prior work BDDs, MTBDDs
• Binary Moment Diagrams (BMDs)
• Construction rules of BMDs
• BMDs - Illustration
• AND, OR, XOR using BMDs
• Word level Operations using BMDs
• Verification using BMDs
• Summary

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Introduction

• Some function representations discussed in this
  course
• Sum of the Product form
• Factored forms
• Truth Table
• Binary Decision Diagrams
• Binary Decision Diagrams
• Simple in representing and manipulating Boolean
  functions
• Reduced Ordered BDDs are canonical (useful for
  verification)
• Drawbacks of BDDs
• Does not handle functions with non-Boolean range
• Bit level representation but specs are in word
  level
• Not good for representing arithmetic operations
• Consider a 32 bit multiplication using BDDs

M Ciesielski, D K Pradhan and A M Jabir,
Decision diagrams for verification, chapter-7,
Practical Design Verification.
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Prior work - BDDs

• Boolean function f decomposed in terms of a
  variable x can be represented by Shannon
  expansion as
• f (x? fx )?? (x ? fx )
• Function decomposed into positive and negative
  co-factors at the node variable x
• fx f(x1)
• fx f(x0)
• BDDs
• Boolean ? Boolean
• Point-wise decomposition (Decision)
• The output is Boolean
• Decision at every node and proceed

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Prior work - MTBDDs

• MTBDDs
• Multi Terminal BDDs
• Extending BDDs to allow integer leaf values
• Point-wise decomposition based on Shannon
  expansion

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Problem Statement

• To find a data structure that can map Boolean
  variables to integers in a compact form
• This helps in representing the arithmetic
  operations
• Word level operations easy to handle
• Ex Bit level Multiplier vs Word level
• Specs are in word level

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Binary Moment Diagrams (BMDs)

• Modified Shannon Expansion
• Boolean variable treated as a binary (0,1)
  integer variable
• Complement of x modeled as (1-x)
• Now the function can be represented as
• f x fx1 (1-x) fx0
• fx0 x (fx1 fx0 )
• fx0 x f?x
• is addition here
• Function is branched into two components
• Constant Component
• Linear Component
• Moment based decomposition

M Ciesielski, D K Pradhan and A M Jabir,
Decision diagrams for verification, chapter-7,
Practical Design Verification.
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Reading Binary Moment Diagrams

• BMDs
• Linear moment decomposition
• Dotted node represents constant moment and solid
  line represents linear moment
• f const var lin_moment
• f k yg
• g 2 4z
• k 8 (-20)z

Bryant,R.E and Chen Y-A. Veri?cation of
arithmetic circuits with binary moment diagrams,
DAC 1995
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Multiplicative BMD (BMD)

• BMDs simply encode the numerical values into
  terminal vertices.
• In a BMD edge weights are used to share any
  common sub-expressions.
• BMDs
• Not decision diagrams as they are based on the
  moment decomposition
• Multiplicative diagrams each path is a product
  of nodes and the edge weights

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BMD reduction rules

• Irredundancy
• When a linear moment of at a node v is 0, the
  function has only a constant term and thus does
  not depend on v.
• Hence node v can be removed.
• Merge the identical sub-graphs
• Similar to BDDs
• Two nodes with same index variable and having
  same two moments can be merged.

M Ciesielski, D K Pradhan and A M Jabir,
Decision diagrams for verification, chapter-7,
Practical Design Verification.
11
Normalization of weights

• Rules imposed on manipulating edge weights to
  make the graph canonical
• Normalized by factoring out gcd of the argument
  weights wgcd(wl(x),wh(x))

Bryant,R.E and Chen Y-A. Veri?cation of
arithmetic circuits with binary moment diagrams,
DAC 1995
12
Illustration - BMD

• f8-20z2y4yz12x24xz15xy
• Variable order (say) x,y,z
• f fx x f?x
• Linear f?x
• Constant fx

82y4yz-20z
1215y24z
8-20z
1224z
4z2
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Illustration - BMD

• f8-20z2y4yz12x24xz15xy
• Variable order (say) x,y,z
• f fx x f?x
• Linear f?x
• Constant fx

1215y24z
82y4yz-20z
2
3
4
2
2
4
5
12
8-20z
1224z
15
4z2
12
4
2
-20
8
24
15
2
-5
1
2
1
2
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Illustration - BMD

• f8-20z2y4yz12x24xz15xy
• Variable order (say) x,y,z
• Introducing the edge weights

82y4yz-20z
1215y24z
2
3
4y2yz-10z
45y8z
4-10z
8z4
2
4
5
2z1
2-5z
2z1
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Illustration - BMD

• f8-20z2y4yz12x24xz15xy
• 8-20z2y (12z) 12x(12z) 15xy
• Variable order (say) x,y,z
• BMD after reduction

2
3
4y2yz-10z
45y8z
2
4
2-5z
5
2z1
2
-5
2
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Illustration BMD and BMD

• Unsigned integer X 8x3 4x2 2x1 x0

Slide taken from Prof. Ciesielskis TED
presentation.
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Representation of Integers

• Unsigned sum of the weighted bits
• Signed Twos complement, Sign-Magnitude

Bryant,R.E and Chen Y-A. Veri?cation of
arithmetic circuits with binary moment diagrams,
DAC 1995
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Decisions Making

• In a real scenario we might still have to make a
  decision at some point (Boolean connectors)
• BMDs will try to implement Boolean in terms of
  arithmetic expression
• MUX y (A (and) s ) OR (B (and) s)

MUL
MUX
MUL
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Representation of Boolean functions

• NOT x (1-x)
• AND x ? y
• OR xy-(x ? y)
• XOR xy-2(x ? y)

X y OR XY
0 0 0 0
0 1 1 1
1 0 1 1
1 1 1 2
-1
-1
-2
NOT
AND
OR
XOR
M Ciesielski, D K Pradhan and A M Jabir,
Decision diagrams for verification, chapter-7,
Practical Design Verification.
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Representation of word level operations - Addition

• SUM XY
• Both X and Y here are 3 bit wide
• X 4x22x1x0 Y 4y22y1y0
• XY (4x22x1x0)(4y22y1y0)
• 4(x2 y2) 2(x1 y1) (x0 y0)
• Linear with number of bits

4
4
2
2
1
1
M Ciesielski, D K Pradhan and A M Jabir,
Decision diagrams for verification, chapter-7,
Practical Design Verification.
21
Bit level representation of addition

• Derived using gate level representation of the
  circuit
• Sum using XORs and carry using AND, OR gates

Bryant,R.E and Chen Y-A. Veri?cation of
arithmetic circuits with binary moment diagrams,
DAC 1995
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Representation of word level operations - Product

• Product XY
• Both X and Y here are 3 bit wide
• X 4x22x1x0 Y 4y22y1y0
• XY (4x22x1x0)(4y22y1y0)
• 4x2 (4y22y1y0) 2x1 (4y22y1y0)
  x0(4y22y1y0)
• Variable order x2x1x0y2y1y0
• Linear with number of bits

4
2
1
4
2
1
M Ciesielski, D K Pradhan and A M Jabir,
Decision diagrams for verification, chapter-7,
Practical Design Verification.
23
Verification using BMDs

• Goal To prove equivalence between the bit level
  circuit and word level specification
• Word level Word level
• Bit level Word level
• Hierarchical
• Circuit output interpreted as word should match
  the specification when applied to word level
  interpretations of the input

Bryant,R.E and Chen Y-A. Veri?cation of
arithmetic circuits with binary moment diagrams,
DAC 1995
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Summary

• BMDs
• Maps Boolean to Integers
• Canonical
• Equivalence check
• Limitations
• Satisfiability
• Cannot be determined directly like in BDDs
• Outputs are integer
• Cannot split output into individual bits
• What if you want to look into a particular output
  bit?

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References

• 1 Bryant,R.E and Chen Y-A. Veri?cation of
  arithmetic circuits with binary moment diagrams,
  DAC 1995
• 2 M Ciesielski, D K Pradhan and A M Jabir,
  Decision diagrams for verification, chapter-7,
  Practical Design Verification

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Thank You!