Demonstration of STDP based Neural Networks on an FPGA

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Demonstration of STDP based Neural Networks on an
FPGA

• Kuldeep Singh

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Overview

• Aim and Motivation
• Problem Statement
• Background
• Related work
• Plan of action

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AIM

• To develop a prototype for demonstrating the
  feasibility of STDP based neural networks before
  chip level implementation.
• To provide configurability to quickly test the
  effectiveness of STDP

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Motivation

• Actual chip level design a lengthy and expensive
  process.
• Simulations in software are very slow.
• Different applications require redesigning of chip

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Problem

• Implementation of neurons, synapses and
  inter-connects on the FPGA.
• Provision for modification of parameters
• Need to alter initial weights of the synapses
• Specification of configuration
• Network topology
• Minimization of FPGA resources usage

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STDP based Learning

• Synaptic weights are modified according to time
  of the spike at the pre-synaptic input.
• Synapses helping to spike are strengthened(LTP)
• Noncontributing synapses are weakened(LTD)

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STDP (continued)

• STDP algorithm

P(t) exp(-t / tp ) and Q(t) exp(-t / tq )
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Related Work

• Design of analog/digital simulator dedicated to
  real-time neurocomputing
• (B. Belhadj et al.)

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Function of Digital hardware

• Get neurons config. parameters from the user send
  them to the ASICs.
• Map the neural network topology
• Give to user the neural state information
• Receive spike events, send the synaptic signals
  to post-synaptic neurons
• Compute STDP and update synaptic weights

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Distribution of computational tasks in the system
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Final Implementation

• 25 neurons in network
• 126 slices used for implementing STDP
• Exponential block is shared in a TDMA manner

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Analysis

• Pros
• Neurons implemented in ASIC
• High density is achieved
• Better replication of neural dynamics
• Lower power consumption
• Cons
• Inflexibility
• Longer design time
• Susceptibility to noise
• Thermal noise
• Power supply variation
• Device variation

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Plan

• Implementation of the neurons, synapses and
  inter-connects on the FPGA.
• Provision for the user to modify the parameters.
• GUI for the user to modify the initial parameters
  and topology
• Testing of the final implementation for various
  testcases.

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Implementation of STDP

• Pre-calculate the synaptic weight changes.
• Implement the full algorithm

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Implementation of a Neuron

• One possibility is to use Sniders neuron model
• Start with the basics and mimic the behavior of
  neuron.

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Thank You

• Questions? Comments? Opinions?