Design and Implementation of the Digital Controller for a Fuel Cell DC-DC Power Converter system - PowerPoint PPT Presentation

1 / 22
About This Presentation
Title:

Design and Implementation of the Digital Controller for a Fuel Cell DC-DC Power Converter system

Description:

design and implementation of the digital controller for a fuel cell dc-dc power converter system o.a. ahmed, j.a.m. bleijs – PowerPoint PPT presentation

Number of Views:112
Avg rating:3.0/5.0
Slides: 23
Provided by: Oday10
Category:

less

Transcript and Presenter's Notes

Title: Design and Implementation of the Digital Controller for a Fuel Cell DC-DC Power Converter system


1
Design and Implementation of the Digital
Controller for a Fuel Cell DC-DC Power Converter
system
Department of Engineering
O.A. Ahmed, J.A.M. Bleijs
2
2
  • presentation Outline
  • Introduction
  • Dynamic Performance of PEMFC
  • FC Converter Features
  • Controller Design
  • Simulation Results
  • Control Algorithm Implementation
  • Converter System Implementation
  • Conclusions

3
  • Introduction

3
DC Microgrid Power System
4
  • Introduction

4
  • DC Microgrid may comprise of
  • A dispatchable power generator, such as the fuel
    cell (FC) or a back-up diesel generator.
  • Non-dispatchable sources, such as solar PV
  • and wind turbines.
  • Energy storage, such as ultra-capacitor or
    battery.
  • The overall efficiency of the distributed system
    depends on efficiency of power electronic
    converters.
  • To obtain a cost-effective converter solution
  • High efficiency.
  • Low cost.
  • Robust control system

5
  • objective

5
Development of a Two-Loop Controller for a High
Efficiency FBCFC for a FC generator
Dynamic Response Analysis and Modeling of a
Ballard Nexa 1.2kW PEMFC
Digital Controller Design Based on a TMS320F2812
DSP
6
  • Dynamic Performance of PEMFC

6
  • Nexa data acquisition system is inadequate to
    show actual response.
  • Fast-acting switches and high speed transducers
    are used.
  • The gross stack current is 1.3 of the nominal
    current.

Experimental Dynamic Response Set-up for PEMFC
7
  • Dynamic Performance of PEMFC

7
Accurate transient response using experimental
set-up
Data log file
8
  • Dynamic Performance of PEMFC

8
Fuel cell model of test with resistive load
9
  • Dynamic Performance of PEMFC

9
Simulated Transient Response of FC model
10
  • FC Converter Features

10
  • The clamp switch gives zero voltage switching
    (ZVS) for all switches at turn on and alleviates
    the usual voltage ringing across the bridge
    switches (S1S4)
  • At turn off the voltage across all switching
    devices is clamped to the capacitor voltage.
  • The output rectifier diodes operate with zero
    current switching (ZCS).
  • Full bridge with voltage doubler technique
    results in reduced voltage across output
    capacitors and diode rectifier.
  • Minimizes the voltage rating of the
    semiconductor devices.
  • Reduces the turn ratio of high frequency
    transformer to half that of the conventional
    FBCFC.
  • Untapped secondary winding transformer
    simplifies the transformer construction, improves
    window utilization, and results in lower leakage
    inductance.

11
  • Controller Design

11
  • Initially an analogue PI was designed for the
    FBCFC based on its small signal transfer
    functions .
  • Digital average current (DAC) mode control and
    predictive current control (PCC) techniques can
    be used for the system.
  • Since FC takes 0.24 second to respond after a
    sudden load application from no-load DAC is
    selected without need for a complex control
    algorithm.

Two-loop PI digital controller
12
  • Controller Design

12
  • The designed digital controller takes into
    account the sampling delay (Hsmp) and the
    computation delay (Hc).
  • Two PI controllers with anti-windup protection
    were designed and their optimal parameters
    obtained using the Control Design Toolbox in
    Matlab.
  • Based on the designed digital controller loop
    for the FBCFC, the transfer function for the
    current, voltage and overall open loop response
    of the system are obtained .

13
  • Controller Design

13
  • The plot indicate that inner loop Cid(z) gain
    has a desired crossover frequency at 5kHz with a
    phase margin of 590.
  • Digital PI parameters for Cid(z) are Kpc
    0.1147, and Kic 506.66.

Bode Plot of Current Controller Open Loop
14
  • Controller Design

14
  • To accommodate the slow FC response, low
    bandwidth is used for voltage loop Cvi(z).
  • The voltage loop has a crossover frequency of
    149Hz and a phase margin of 58.70.
  • Digital PI parameters for Cvi(z) are Kpv
    1.08625,
  • Kiv 100.748

Bode Plot of Voltage Controller Open Loop
15
  • Controller Design

15
  • Due to the active clamp the resonance is
    absence.
  • The plots show that the bandwidth and phase
    margin of the controller system are designed as
    desired.

Bode Plot of Overall Open Loop System
16
  • simulation results

16
  • The simulated dynamic response of the converter
    at sudden load changes shows that the voltage
    recovers to its steady-state value within 15m
    sec.

Output voltage waveform during load changes
  • Designed PI digital controller has been
    implemented in a DSP the on-chip ADC converter,
    PWM compare function and other functions were
    emulated in Simulink.

17
  • control algorithm implementation

17
  • IQ math library in CCS is used for the PI
    compensators, ADC results and ADC and PWM scaling
    factors.
  • The number of GP timers in a DSP is limited to
    four. The PWM signals for all switches are
    generated using only one GP timer with dead-band
    zone.

Flow chart of the overlap PWM algorithm for FBCFC
18
  • control algorithm implementation

18
Software block diagram of 32-bit PI digital
control for voltage and current loop
19
  • converter system implementation

19
  • The sampling frequencies are chosen 20 kHz for
    the current-loop and 2.5 kHz for the voltage-loop
    controllers.
  • The FBCFC without clamp circuit shows high
    voltage overshoots across the MOSFETs resulting
    in increase switching and conduction losses and
    reducing the converters efficiency.

FBCFC with voltage doubler but without clamp
circuit secondary voltage (ch3), drain-source
voltage across S1 (ch4)
Proposed FBCFC primary voltage (ch3), FC current
(ch4), clamp switch voltage (ch2)
20
  • converter system implementation

20
Simulated and Experimental Converter Efficiency
21
  • conclusions

21
  • FC experiments showed that the number of
    measurement points using Nexa log file is not
    sufficient to plot the accurate transient
    response characteristics of the FC stack. It is
    observed that the modelled FC matches very well
    with the real FC system results
  • A two-loop digital controller with anti-windup
    protection has been developed for a 1.2kW active
    clamp FBCFC topology with a voltage doubler.
  • The experimental results have validated the
    accurate modelling for the FC converter system.
  • Simulation and practical measurements of the
    proposed converter and other configurations at
    different loads have shown that the proposed
    configuration has the highest efficiency.

22
THANK YOU FOR LISTENING
Write a Comment
User Comments (0)
About PowerShow.com