Instruction Set Architecture of MIPS Processor Presentation B

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CSE 675.02 Introduction to Computer Architecture
Instruction Set Architectureof MIPS Processor
Presentation B
Slides by Gojko Babic
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MIPS Processor
Figure A.10.1
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MIPS Registers

• CPU

32 32-bit general purpose registers GPRs (r0
r31)
r0 has fixed value of zero. Attempt to writing
into r0 is not illegal, but its value will not
change

• two 32-bit registers Hi Lo, hold results of
  integer
• multiply and divide

• 32-bit program counter PC

• Floating Point Processor FPU (Coprocessor 1
  CP1)

32 32-bit floating point registers FPRs (f0
f31)
five control registers
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MIPS Registers (continued)

• Coprocessor 0 CP0 is incorporated on the MIPS
  CPU chip
• and it provides functions necessary to support
  operating
• system exception handling, memory management
  scheduling
• and control of critical resources.

• Coprocessor 0 (CP0) registers (partial list)

Status register (CP0reg12) processor status
and control
Cause register (CP0reg13) cause of the most
recent exception
EPC register (CP0reg14) program counter at
the last exception

• BadVAddr register (CP0reg08) the address for
  the most
• recent address related exception

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MIPS Data Types

• MIPS operates on

32-bit (unsigned or 2s complement) integers,
32-bit (single precision floating point) real
numbers,
64-bit (double precision floating point) real
numbers

• bytes and half words loaded into GPRs are
  either zero or sign
• bit expanded to fill the 32 bits

• only 32-bit units can be loaded into FPRs
  32-bit real numbers
• are stored in even numbered FPRs.

• 64-bit real numbers are stored in two
  consecutive FPRs,
• starting with even-numbered register.

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MIPS arithmetic

• All instructions have 3 operands
• Operand order is fixed (destination
  first) Example C code a b c MIPS
  code add a, b, c The natural
  number of operands for an operation like addition
  is threerequiring every instruction to have
  exactly three operands, no more and no less,
  conforms to the philosophy of keeping the
  hardware simple

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MIPS arithmetic

• Design Principle simplicity favors regularity.
  
• Of course this complicates some things... C
  code a b c d MIPS code add a, b,
  c add a, a, d
• Operands must be registers, only 32 registers
  provided
• Each register contains 32 bits
• Design Principle smaller is faster. Why?

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Registers vs. Memory

• Arithmetic instructions operands must be
  registers, only 32 registers provided
• Compiler associates variables with registers
• What about programs with lots of variables

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Memory Organization

• Viewed as a large, single-dimension array, with
  an address.
• A memory address is an index into the array
• "Byte addressing" means that the index points to
  a byte of memory.

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MIPS Addressing Modes

• register addressing

• immediate addressing

• only one memory data addressing

register content plus offset (register
indexed)

• since r0 always contains value 0

r0 offset ? absolute addressing

• offset 0 ? register indirect

• MIPS supports byte addressability

it means that a byte is the smallest unit with
its address

• MIPS supports 32-bit addresses

• it means that an address is given as 32-bit
  unsigned
• integer

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Memory Organization

• Bytes are nice, but most data items use larger
  "words"
• For MIPS, a word is 32 bits or 4 bytes.
• 232 bytes with byte addresses from 0 to 232-1
• 230 words with byte addresses 0, 4, 8, ... 232-4
• Words are aligned i.e., what are the least 2
  significant bits of a word address?

Registers hold 32 bits of data
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MIPS Alignment

• MIPS restricts memory accesses to be aligned as
  follows

32-bit word has to start at byte address that
is multiple of 4
32-bit word at address 4n includes four bytes
with addresses 4n, 4n1, 4n2, and 4n3.
16-bit half word has to start at byte address
that is multiple of 2
16-bit word at address 2n includes two bytes
with addresses 2n and 2n1.
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MIPS Instructions

• 32-bit fixed format instruction and 3 formats

• register register and register-immediate
  computational
• instructions

• single address mode for load/store
  instructions register content offset
  (called base addressing)

• simple branch conditions
• branch instructions use PC relative
  addressing
• branch address PC 4 4offset

• jump instructions with
• 28-bit addresses (jumps inside 256 megabyte
  regions),
• or
• absolute 32-bit addresses.

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Our First Example

• Can we figure out the code? Guess!!!

swap(int v, int k) int temp temp
vk vk vk1 vk1 temp
swap muli 2, 5, 4 add 2, 4, 2 lw 15,
0(2) lw 16, 4(2) sw 16, 0(2) sw 15,
4(2) jr 31
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MIPS Instruction (continued)

• Instructions that move data
• load to register from memory,
• store from register to memory,
• move between registers in same and different
  coprocessors

• ALU integer instructions,

• Floating point instructions,

• Control-related instructions,

• Special control-related instructions.

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Stored Program Concept

• Instructions are bits
• Programs are stored in memory to be read or
  written just like data
• Fetch Execute Cycle
• Instructions are fetched and put into a special
  register
• Bits in the register "control" the subsequent
  actions
• Fetch the next instruction and continue

memory for data, programs, compilers, editors,
etc.
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MIPS Instruction Layout

• MIPS instructions are an example of fixed
  field decoding

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CPU Load Store Instructions

• lw rt, offset(rs) load 32-bits
• Regsrt ? Mem offsetRegsrs

• sw rt, offset(rs) store 32-bits
• Mem offsetRegsrs ? Regsrt

• lb rt, offset(rs) load 8-bits (byte)
• Regsrt ? 24-bit sign-extend Mem
  offsetRegsrs

Note means concatenation.

• lbu rt, offset(rs) load 8-bits (byte)
  unsigned
• Regsrt ? 24-bit zero-extend Mem
  offsetRegsrs

• sh rt, offset(rs) store 16-bits
• Mem offsetRegsrs ? Regsrt
• (16 least significant bits
  taken from the register)

Plus sb, lh, lhu
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FP Load, Store Move Instructions

• lwc1 ft, offset(rs) load into FP register
• Regsft ? Mem offsetRegsrs

• swc1 ft, offset(rs) store from FP register
• Mem offsetRegsrs ? Regsft

• mov.d fd, fs move FP double precision between
  FPRs
• Regsfd Regsfd1? Regsfs
  Regsfs1

• mov.s fd, fs move FP single precision between
  FPRs
• Regsfd ? Regsfs

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Move Instructions

• mfc1 rt, fs move from FPU to CPU Regsrt ?
  Regsfs

• mtc1 rt, fs move from CPU to FPU Regsfs ?
  Regsrt

• mfc0 rt, rd move from CP0 to CPU Regsrt ?
  CP0Regsrd

• mtc0 rt, rd move from CPU to CP0 CP0Regsrd
  ? Regsrt

• mfhi rd move from Hi Regsrd ? Hi

• mflo rd move from Lo Regsrd ? Lo

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ALU Integer Instructions

• add rd, rs, rt add integer_at_ Regsrd ?
  Regsrs Regsrt

Note Instructions flagged by _at_ may cause an
arithmetic exception.

• addi rt, rs, immediate add immediate
  integer_at_
• Regsrt ? Regsrs 16-bit sign-extend
  immediate

• and rd, rs, rt bit-wise AND 32 bits
• Regsrd ? Regsrs AND Regsrt

• andi rt, rs, immediate bit-wise AND immediate
  32 bits
• Regsrt ? Regsrs AND 16-bit zero-extend
  immediate

• slt rd, rs, rt set less than integer
• if (Regsrs lt Regsrt) then Regsrd ? 1
  else Regsrd ?0

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ALU Integer Instructions (continued)

• mul rs, rt multiply integer Hi Lo?
  Regsrs Regsrt
• Note mul does not generate an arithmetic
  exception, since
• a storage for the result is always
  sufficiently large.

• div rs, rt divide integer Lo ? Regsrs /
  Regsrt
• Hi ?
  Regsrs mod Regsrt
• Note div does not generate an arithmetic
  exception and
• software should test for zero divisor.

• sll rd, rt, shamt shift left logical
• Regsrd ?
  Regsrt ltlt shamt

• lui rt, immediate load upper immediate
• Regsrt ?
  immediate 16 zero-bits

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ALU Integer Instructions (continued)

• addu rd, rs, rt add unsigned integer
• Regsrd ? Regsrs Regsrt

Note This instruction does not cause an
arithmetic exception.
Plus addiu, sub _at_, subu, mulu, divu, or, ori,
xor, xori, nor, slti, sltu, sltiu,
srl, sra

• Instructions addu, addiu, subu, mulu, divu, sltu,
  and sltiu operate on unsigned numbers and these
  instructions do not trap on overflow. They are
  appropriate for unsigned arithmetic, such as
  address arithmetic, or in integer arithmetic
  environment that ignores overflow, such as C
  language arithmetic.

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Arithmetic FP Instructions

• add.d fd, fs, ft FP double precision add
• RegsfdRegsfd1?
• ?RegsfsRegsfs1
  RegsftRegsft1

• mul.s fd, fs, ft FP single precision
  multiply
• Regsfd? Regsfs Regsft

Plus add.s, sub.d, sub.s, mul.d, div.d, div.s,
several convert floating point to/from
integer instructions, several compare
instructions.
Note Any of instructions above may cause FP
exception.
All instructions presented so far, in addition,
increment the program counter PC by 4, i.e.
PC ? PC 4
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Control Related Instructions - Jumps

• jr rs jump register PC ? Regsrs

• jalr rs,rd jump and link register
• Regsrd ? PC4 PC ? Regsrs

• j jump_target jump inside 256 MB region
• PC low order 28 bits ? jump_target 2
  zero-bits

• jal jump_target jump inside 256 MB region
  and link
• Regs31 ? PC4
• PC low order 28 bits ? jump_target 2
  zero-bits

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Control Related Instructions - Branches

• beq rs, rt, offset branch on equal
• if (Regsrs Regsrt)
• then PC? PC4 14-bit sign extend offset
  2 zero-bits
• else PC?PC4

• bne rs, rt, offset branch on not equal
• if (Regsrs ! Regsrt)
• then PC?PC4 14-bit sign extend
  offset 2 zero-bits
• else PC?PC4

• bgez rs, offset branch on greater or equal
  zero
• if (Regsrs 0)
• then PC?PC4 14-bit sign-extend offset
  2 zero-bits
• else PC?PC4

Plus bgtz, blez, bltz
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Illustration of MIPS Addressing Modes
offset
offset
jump_target
Figure 2.24
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Special Control - Related Instructions

• syscall to cause a syscall exception
• Encoding 000000 00000000000000000000 001100

• break to cause a break exception
• Encoding 000000 00000000000000000000 001101

• teq rs, rt trap exception if equal if
  (Regsrs Regsrt)
• 
  then trap exception

• tlti rs, immediate trap exception if less
  than immediate
• if (Regsrs lt
  48-bit sign-extend immediate
• then trap exception

• eret return from exception

Plus several additional conditional trap
instructions
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CPU Modes and Address Spaces
There are two processor (CPU) modes of operation

• Kernel (Supervisor) Mode and

• User Mode

The processor is in Kernel Mode when CPU mode bit
in Status register is set to one. The processor
enters Kernel Mode at power-up, or as result of
an interrupt, exception, or error.
The processor leaves Kernel Mode and enters User
Mode when the CPU mode bit is set to zero (by
some instruction).
Memory address space is divided in two ranges
(simplified)

• User address space

addresses in the range 0 7FFFFFFF16

• Kernel address space

addresses in the range 8000000016 FFFFFFFF16
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Privilege Instructions
When operating in User Mode, processor has access
only to the CPU and FPU registers, while when
operating in Kernel Mode, processor has access
to the full capabilities of processor including
CP0 registers.
Privileged instructions can not be executed when
the processor is in User mode, i.e. they can be
executed only when the processor is in Kernel
mode

• Examples of MIPS privileged instructions
• any instruction that accesses Kernel address
  space,
• mfc0 move word from CP0 to CPU,
• mtc0 move word to CP0 from CPU,
• lwc0 load (from memory) word into CP0,
• swc0 store (into memory) word from CP0.

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MIPS Exceptions A Subset
There are four sets of causes for an exception.
A. Exceptions caused by hardware malfunctioning

• Machine Check Processor detects internal
  inconsistency

• Bus Error on a load or store instruction, or
  instruction fetch

• B. Exceptions caused by some external causes (to
  the processor)
• Reset A signal asserted on the appropriate pin

• NMI Non-maskable interrupt serious hardware
  problems

• Hardware Interrupts Six hardware interrupt
  requests can be
• made via asserting signal on any of 6 external
  pins.
• Hardware interrupts can be masked by setting
  appropriate bits
• in Status register

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Exceptions by External Causes
Reset
IRQ 1
NMI
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MIPS Exceptions A Subset (continued)
C. Exceptions that occur as result of instruction
problems

• Address Error a reference to a nonexistent
  memory segment,
• or a reference to Kernel address space from
  User Mode

• Reserved Instruction A undefined opcode field
  (or privileged
• instruction in User mode) is executed

• Integer Overflow An integer instruction results
  in a 2s
• complement overflow

• Floating Point Error FPU signals one of its
  exceptions, e.g.
• divide by zero, overflow, and underflow)

• D. Exceptions caused by executions of special
  instructions
• Syscall A Syscall instruction executed

• Break A Break instruction executed

• Trap A condition tested by a trap instruction
  is true

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MIPS Exception Processing
When any of the exceptions previously listed
occur, the MIPS processor processes the exception
in the following 3 steps
Step 1.

• EPC register gets a value equal to either

address of a faulty instruction if the
instruction itself caused exception (e.g.
address error, reserved instruction) or
detected hardware malfunctioning (e.g. bus
error),
address of the next instructions which would
have been executed, in all other cases.
Additionally, in the case of the address error,
BadVAddr register gets value of the invalid
address.
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MIPS Exception Processing (continued)
Step 2. (Simplified)

• PC ? 8000018016

next instruction executed is at the location
8000018016

• Cause register ? a code of the exception

• Each exception has its code, e.g.
• hardware interrupt 0
• illegal memory address (load/fatch or store)
  4 or 5
• bus error (fetch or load/store) 6 or 7
• syscall instruction execution 8
• illegal op-code, i.e. reserved or undefined
  op-code 10
• integer overflow 12
• Floating point exception 15

Step 3.

• Processor is now in Kernel mode, i.e. CPU mode
  bit ? 1

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Dual-Mode of CPU Operation

• CPU mode bit added to computer hardware to
  indicate the current CPU mode 1 (kernel) or 0
  (user).
• When an exception or interrupt or fault occurs
  CPU hardware switches to the kernel mode.

Privileged instructions can be executed only in
kernel mode.
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• Problem OS loads the exception handling routine
  at the address 8100 000816. What else should be
  done so this routine is activated each time an
  exception happens? Your solution should include
  instructions.

• Answer Memory location 8000018016 should
  contain instruction j 40000216 i.e.
• mem location 80000180 ? 000010 00 0100 0000
  0000 0000 0000 0010
• 
  j 0 4 0 0 0
  0 2
• Effect of j instruction PC ? PC31..28
  I25..0 02
• PC ? 1000 0001 0000 0000 0000 0000 0000 1000
• 8 1 0 0
  0 0 0 8

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• Comments
• sll instruction is noop instruction
• Add srav, srlv, sllv
• mention two branch and link instructions
• consider adding few fp instructions.