ESODAC Study for a new ESO Detector Array Controller

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ESODACStudy for a new ESO Detector Array
Controller
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Introductionand Key Points

• Idea is to realize a modular system with a basic
  Front-end unit for a four channel system on one
  card of standard VME 6U size.
• Power Consumption on Front-end less than 10
  Watts.
• Very low noise design anticipated.
• Add on cards are 32 channels on a board of the
  same size and additional 10 Watts of power
  consumption.
• ( Number of channels can be remotely set ).
• There will be no processor on the front-end side.
• Data distribution on backend side possible free
  topology .
• Connection between Back and Front-end only by
  fibers.
• Weight below 1 Kg.
• This system should not require active cooling.

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System Design
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System Block
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Back-end

• Function is based on the XILINX Virtex Pro FPGA
  XC2VP7 FF 672 .
• Back-End PCI is a 64 Bit PCI board downscale to
  32 Bit PCI possible.
• FPGA contains PCI interface, protocol engine PCI
  to transceivers
• for communication and data reception and
  RocketIO transceivers.
• Direct interface from FPGA to PCI without glue
  logic.
• Independent PCI master and PCI slave.
• Communication and data transfers all on serial
  link.
• Data rate on one channel between front and
  back-end 200MByte
• More bandwith possible ( one FPGA contains 8
  transceivers space limit for PCI card size
  might be four ).
• Routing capability by high speed fibers e.g. to
  VME or other systems.
• Selective data reception and routing possible (
  like in old times shift and add with IRACE ).

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Front-End Basic Module

• The front-end Basic Module is based on the XILINX
  Virtex Pro FPGA XC2VP7 FF 672.
• Main functions of this module are
• Communication
• Data transfer
• Sequencer
• Clock driver, biases and associated DACs
• Four data acquisition channels ( each either 16
  or 18 Bit ADCs ) and preamps
• Utilities ( Markers, Synchronization )
• Telemetry

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Front-End Basic Module

• Design ideas are
• Communication and data transfer to the back-end
  is handled with the FPGAs Gigabit transceivers.
• Protocol engine to serial link contained within
  the FPGA.
• Sequencer is completely contained within the
  FPGA.
• The digital clock driver lines of the sequencer
  connect out of the FPGA without glue logic to the
  clock driver switches. Clock driver alternatives
  have to be evaluated, one possibility is type
  used in IRACE.
• Sequencer will contain provisions for high speed
  external trigger inputs and status outputs.
• The ADC outputs of the four acquisition channels
  connect without glue logic to the FPGA due to the
  high pin count available there. Favorable ADCs
  are the AD76xx types from Analog Devices. The
  preamplifier is fully differential, input range
  will be /- 2.5V. There will be no clamp/sample
  implemented in the analog chain.
• Provisions will be taken to incorporate different
  ADC types ( e.g. high speed lower resolution
  types) .

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Front-End Basic Module (cont)

• Design ideas are
• Synchronization will be foreseen to additional
  Basic Modules (more clocks, biases).
• For high-drive clocks (e.g. high capacitive loads
  by big arrays) provisions to external drive
  modules must be foreseen.
• Connection to the additional multi channel AQ
  modules is a connection by fiber or copper on
  high speed links with FPGA transceivers. This
  would give a very low data bus noise coupling to
  the analog part. Communication and set-up of
  front-end modules also runs on this link.
• Alternatively possible could be connection by a
  64 Bit bus. The bus principle is a daisy chain as
  in IRACE. This bus will directly sort out of the
  FPGA without glue logic. Different driver
  possibilities (LVTTL, GTL ) are provided within
  the FPGA. A low speed serial bus connecting all
  front-end modules needed for set-up and tests
  would also sort out of the FPGA.
• Provisions for adaptation to detector ASICs must
  be foreseen ( at present missing protocol
  definition of ASIC).
• Telemetry will be on board.
• Digital Outputs for shutter control, test markers
  
• Monitoring of clocks, biases and detector signals
  will be on basis of an external module.

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Front-End Basic Module
Connectors for detector signals, clocks and
biases have to be defined.
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Add on cards

• AQ Module ( 16 Bit )
• The front-end AQ Module is based on the XILINX
  Virtex Pro FPGA XC2VP7 FF 672.
• On board are 32 acquisition channels on 16 Bits.
• ADC outputs of the acquisition channels connect
  with little glue logic on a bus structure to the
  FPGA (tests on crosstalk are needed).
• Favorable ADCs are the AD76xx types from Analog
  Devices.
• The preamplifier is fully differential, input
  range will be /- 2.5V. There will be no
  clamp/sample implemented in the analog chain.
• A low speed serial bus for set-up and test must
  be implemented. AQ modules are always slaves on
  this bus.
• AQ Module ( 18 Bit )
• On the basis of the 16 Bit AQ module a 18 Bit
  version can be build. Same layout and printed
  board might be possible.
• High Drive Module
• External Monitor

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Status
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Back-end

• Back-end Prototype ( PCI 64 Bit board ) designed
  in scheme and layout.
• FPGA design (Communication and Scatter-Gather DMA
  in 32 Bit functional)
• Fiber optics system realized as functional study.

PCI 64 Bit Design ( DXP Image )
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Front-end

• Fiber optics system realized as functional study.
• Sequencer realized as functional study.
• Acquisition module ( Adcs and preamp ) are
  already tested as a piggy-back back-up monolithic
  replacement for the Analogic hybrid ADCs. Preamp
  will have to be revised (single ended gt
  symmetrical).
• Clock driver could be realized like IRACE module
  alternatives have to be studied.
• If not implemented by high speed links
• Bus system mixture between IRACE ( daisy chain)
  and Compact PCI.
• Neither studies nor design.
• Power supply design not studied. Separate and
  remote from Front-end desired.